Fujitsu at 90 nm tells us something about 65 nm CPUs

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Fujitsu was also present to outline their next-generation SPARC64 processor: SPARC64 VI. Code named Olympus and due to arrive late in 2005 or early 2006, the chip features dual cores and is expected to clock at 2.4 GHz at 0.09µ. Weighing in at 690 million transistors, Olympus will sport a 6 MB on-chip L2 cache as well as a 256 KB L1 cache (128 KB Instruction, 128 KB Data). SPARC64 VI appears to be a dual-core variant of SPARC64 V, and therefore does not seem to be based upon an entirely new core design.

They can be big and run pretty fast ( as I said other times not all the CELL chip has to clocked high... multiple clock domains [I know people will try to see how this relates to CELL and I gave a small answer to that here linking to an argument I already made in this forum in the not so remote past] ) if enoug attention is dedicated to heat extraction and dissipation.
 
Why don't you highlight the release date? Also, that thing is likely going to be pretty expensive and who knows what kind of cooling it'll require.
 
PlayStation 3 will require some neat cooling as well and IMHO SCE and Toshiba are working hard on the heat extraction and dissipation issue, much harder than what people are expecting them to do.

I am sure people imagine them just slapping some normal heatsink + fan and that is it, but I don't agree with this view.

PlayStation 3 will use 65 nm technology with a 45 nm die shrink expected relatively soon ( Toshiba is building the 65 nm lines with the 45 nm shift in mind ) and that indicates the chips used will be big.

I am not asking for a 1.4 BTransistors CELL CPU, just pointing out that 500-800+ MTransistors ( or even 1 BTransistors, but this is the upper limit of my prediction ) on a 65 nm process is not unfeasible.

ATI can pack 100+ MTransistors with 150 nm technology after-all.

Also I do not believe PlayStation 3 will be released befor late 2005 which will be the fruit of many years of development and hard work on state of the art manufacturing processes and materials.
 
Panajev2001a said:
Fujitsu was also present to outline their next-generation SPARC64 processor: SPARC64 VI. Code named Olympus and due to arrive late in 2005 or early 2006, the chip features dual cores and is expected to clock at 2.4 GHz at 0.09µ. Weighing in at 690 million transistors, Olympus will sport a 6 MB on-chip L2 cache as well as a 256 KB L1 cache (128 KB Instruction, 128 KB Data). SPARC64 VI appears to be a dual-core variant of SPARC64 V, and therefore does not seem to be based upon an entirely new core design.

They can be big and run pretty fast ( as I said other times not all the CELL chip has to clocked high... multiple clock domains [I know people will try to see how this relates to CELL and I gave a small answer to that here linking to an argument I already made in this forum in the not so remote past] ) if enoug attention is dedicated to heat extraction and dissipation.

You fail to mention the new p4s that were designed to clock high having horrible yields and being pushed back over 4 months . That was also made on .9 micron.

Just because its expected to hit 2.4 ghz doens't mean it will. Give this another post when it actually hits 2.4 ghz and also post the price
 
Panajev2001a said:
PlayStation 3 will require some neat cooling as well and IMHO SCE and Toshiba are working hard on the heat extraction and dissipation issue, much harder than what people are expecting them to do.


asking....but is there any place i can read about that? also didnt you say PS3 will have quality pixel shaders/filtering/FSAA and whatnot, any links to that too? also you mentioned that PS3 will have easier high level devtools to make games, where did you get that from(coz i remember some Sony guy just laughed off when asked about the programming aspect of PS3 "crazy architecture")?
 
Price of that Fujitsu part will not be relevant related to CELL.

Many things changes when your expected volume production is limited to some thousands chips per year or several millions or even tens of millions.

Things that do not make sense suddenly do and a good loss will be taken initially.

I am not asking for a 1+ Billion Transistors, although it is not out of the realm of possibility I have to admit, but for somethign that ranges from 500-800 MTransistors.

Also that chip's L2, L1, OOOe logic, Register file, execution units, internal busses, etc... are supposed to operate at 2.4 GHz.

When talking about CELL I do not see that: the only thing going at ~4 GHz will be the APUs' Register file and execution units ( not the SRAM basd LS ).

The busses and the e-DRAM would be ideally clocked at 1 GHz or 500 MHz using DDR signalling techniques ( same effective bandwidth ).

LS would probably run at 2 GHz or it could run at 1 GHz transferring data in DDR mode.
 
Panajev2001a:

> just pointing out that 500-800+ MTransistors ... on a 65 nm process is
> not unfeasible.

Feasibility depends on the application. SPARCs are meant for a completely different market where price isn't the main concern and noise no concern at all.

Sony and Toshiba may be working on a new cooling solution as you speculate but that only adds to the price of a product that already sounds like it's going to be pretty damn expensive to make.
 
Paul, Panajev, Vince.. what happens if there are considerable delays in getting to 65nm technology on the part of Sony, Toshiba and the world.

There were problems getting to 130nm technology for some players in the market, so it could happen. Relying on a die shrink and technology to advance at a predicted rate is a very dangerous move (see NVIDIA).

I ain't bashing but we live in the real world.... anything can happen.
 
I really don't see the point and relevence of this topic relating to CELL. It doesn't prove or disprove anything about CELL.

I am not asking for a 1+ Billion Transistors, although it is not out of the realm of possibility I have to admit, but for somethign that ranges from 500-800 MTransistors.

Um..nobody ever said 500-800 million transistors was impossible in the CELL chip. As a matter of fact if CELL is supposed to have 32MB of eDRAM then it will have to be at least 500 million transistors including logic.
 
chaphack said:
Panajev2001a said:
PlayStation 3 will require some neat cooling as well and IMHO SCE and Toshiba are working hard on the heat extraction and dissipation issue, much harder than what people are expecting them to do.


asking....but is there any place i can read about that? also didnt you say PS3 will have quality pixel shaders/filtering/FSAA and whatnot, any links to that too? also you mentioned that PS3 will have easier high level devtools to make games, where did you get that from(coz i remember some Sony guy just laughed off when asked about the programming aspect of PS3 "crazy architecture")?

With the power of any of the three next-generation consoles I do not see AA and Pixel Shading to be an issue for any of the three big console makers.

When I mentioned the tool-set and the libraries provided to layStation 3 developers as being easier for them to use than what they were given for initial PlayStation 2 development comes from several small facts: PSP shows that SCE is not stubborn and can go in a direction that helps prorammers ( PSP development resembling more PSOne development which everyone seemed to like ), developers will go crazy if nothing is done to abtract some of the lower level functionality from them andit i a rumor that seems quite persistent as it makes sense.

This would not move the release date of the console forward instead it could be one of the main reasons behond a Q4 2005 launch fo PlayStation 3.
 
Thanks Panajev - could you post the link? Just as a formality, so I can look at the whole article.

You've got me convinced that 500 million+ at 65nm presents no technical problem, and even 1 billion is possible. However, I think we need to look at the economics too. Even after considering the shift to 45nm, I think we'll be constrained by cost. Heat shouldn't be that big of a problem, for reasons discussed in the Clearspeed thread. Besides, no one is better suited to solve that problem than Sony, which has plenty of experience in cooling from their studio audio equipment, and their electromechanical engineering is second to none. (The bipetal robot they have comes to mind - check out those fully-jointed hands!)

I guess the question shifts from, "is it physically possible?" to "when and if it is economically feasible?". That's the next project ;)

Last thing:
When Fujitsu says they can hit 2.4Ghz, and there isn't a compelling, clear reason why they can't, I'm inclined to trust them. Considering that there are already 2.4 Ghz chips, I don't see why this is unbelieveable to some.
 
Paul, Panajev, Vince.. what happens if there are considerable delays in getting to 65nm technology on the part of Sony, Toshiba and the world.

then PS3 will be delayed.

There were problems getting to 130nm technology for some players in the market, so it could happen. Relying on a die shrink and technology to advance at a predicted rate is a very dangerous move (see NVIDIA).

to be fair, the console market doesn't exactly rely on the same price/yield model for it's products.


I ain't bashing but we live in the real world.... anything can happen.

ditto.
 
cybamerc said:
Panajev2001a:

> just pointing out that 500-800+ MTransistors ... on a 65 nm process is
> not unfeasible.

Feasibility depends on the application. SPARCs are meant for a completely different market where price isn't the main concern and noise no concern at all.

Sony and Toshiba may be working on a new cooling solution as you speculate but that only adds to the price of a product that already sounds like it's going to be pretty damn expensive to make.

It will not be cheap, but the high production volumes prjected for a console like PlayStation 3 and the strong efforts in making the technology cheaper by pursuing advances in lithography ( the 45 nm die shrink with full SOI solution will considerably reduces CELL chips sizes [e-DRAM will be considerably smaller moving to a process that allows to remove DRAM's capacitors] ) will make that kind of loss one of the nicest investments SCE and Toshiba could make.

Tahir, IMHO delays on the 65 nm lines becoming fully operative is not the biggest concern right now ( Toshiba should start mass-production fromthe new 65 nm lines on Oita #2 around Septmeber of next-year ): CELL software development is.
 
Panajev2001a said:
With the power of any of the three next-generation consoles I do not see AA and Pixel Shading to be an issue for any of the three big console makers.

When I mentioned the tool-set and the libraries provided to layStation 3 developers as being easier for them to use than what they were given for initial PlayStation 2 development comes from several small facts: PSP shows that SCE is not stubborn and can go in a direction that helps prorammers ( PSP development resembling more PSOne development which everyone seemed to like ), developers will go crazy if nothing is done to abtract some of the lower level functionality from them andit i a rumor that seems quite persistent as it makes sense.

This would not move the release date of the console forward instead it could be one of the main reasons behond a Q4 2005 launch fo PlayStation 3.


you know im no 3D guy, so i be asking on...

Im just thinking that AA and shaders algorithm/hardware in 3yrs time will be more advanced than today, you be thinking all 3 systems will be able to run them and run them well? I mean, if you take todays AA/shaders, next gen should run them at full blast. But will nextgen systems keep pace and implement AA/shaders of the future?

Im asking that because of ATI Orton's "different approach/pixel of polygons" words keep popping into my mind. Seeing the PS2(which trades some features for others) and Cell, i would incline to think that Sony ideals are indeed different.. ?

As for PSP, it seems like a minor extension and modification of PS2 architecture, but Cell sounds like a major upgrade. Hell, how much can you pack in a handheld either way. No?
 
PSP looks like GCN's twin brother and not really like PlayStation 2.

About Orton's comments, I see no issues with lots of very small polygons and Software driven Shaders in terms of Image Quality :)


About the cost issue even after the 45 nm shrink arives, let me remind you of this: the process SCE and Toshiba want to use for the 45 nm node is full SOI and the DRAM cells will not need to have a capacitor and their size will be then reduced even further than what simple scaling due to the shrink to 45 nm technology.

The size of the chip, which is supposed to have a non trivial amount of e-DRAM in it, will be probably almost 55% of its original size ( very rough estimate that tries to take into account the lack of capacitors in the DRAM cells [which would decrease the area taken by each DRAM cell] ).
 
Oh btw isn't this Fujitsu chip using 6.5 MB of SRAM??? How does standard SRAM compare to SONY/Toshiba's eDRAM with regards to size and transistor counts. Would 32MB of eDRAM take up the same amount of space as 6.5MB of standard SRAM??? More? Less?
 
V3 said:
I want to know the size and wattage of that thing.

As the architect said: "concordantly, while your first question maybe the most pertinent you may or may not realize it is also the most irrelevant".

:p

I will try to look for it :)
 
Panajev2001a said:
V3 said:
I want to know the size and wattage of that thing.

As the architect said: "concordantly, while your first question maybe the most pertinent you may or may not realize it is also the most irrelevant".

:p

I will try to look for it :)

It's pretty relevant if you need to put it in a freezer to keep it from frying itself :p
 
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