Feasibility of a 8-Core PowerVR SGX GPU.

[Capeta]

Can the SGX cores be tiled like previous PowerVR GPUs without memory duplication? How big would an 8 core SGX be in terms of die area using 65nm? Also is SGX backards compatible with CLX2 graphics libraries?

 

[Techno+]

u mean shader cores?, i've been trying to find out the die areas since 2-4 months, i read somewhere at 90 nm or 130 nm (cant remember) it takes up 2-10 mm square.

 

[Capeta]

What I mean is each core rendering 1/8 of a screen. Does the memory need to be duplicated like the old PowerVR cores since it's a TBDR.

 

[Lazy8s]

SGX is the name of a whole series of configurations that cover from portable to desktop, so an eight-"pipeline" core could be used instead of grouping eight cores, although grouping multiple cores is likely always an inherent possibility (whether or not the memory is duplicated is probably a design choice with trade-offs either way.)

Like the generational relationships of other company's GPUs, SGX isn't directly backwardly compatible with CLX2.

Imgtec's website has product information:

http://www.imgtec.com/powervr/products/Graphics/SGX/index.asp

 

[Rainbow Man]

Why would you duplicate a 3D chip without duplicating its attached memory when just one 3D chip can use all the memory speed it can get?

Sounds like a poorly thought through idea to me.

Peace.

 

[amk]

Also is SGX backards compatible with CLX2 graphics libraries?

There are some features of CLX2 that have been dropped, such as modifier volumes and VQ texture compression (I think that was what it was called...).

Also, I believe I am correct in saying fixed-function operations available to PowerVR series 2 would have to be done by series 5 using shaders, much as is the case with NVidia and ATi hardware.

So no. Even emulation is a problem. No playing Dreamcast Soul Calibur in HD with 8X FSAA and 16X anisotropy .

 

[Lazy8s]

Data duplication is the kind of duplication being discussed; the Naomi2 arcade board, which used two PowerVR graphics chips, stored the same data in the VRAM of each.

That kind of design was probably made by choice based upon the particulars of Naomi2's development as opposed to being some requirement of a PowerVR architecture.

 

[Capeta]

Ok thanks for the information. Another question regarding an "8 pipeline" SGX. Would each pipeline be rendering 1/8 of the screen or would all pipelines be dedicated to rendering each tile sequentially?

 

[Lazy8s]

Only one tile is rendered at a time per core, so all pipelines/execution units work together on tiles sequentially.