Digitimes: Nvidia said to debut NV30 at Comdex

[martrox]

Digitimes: Nvidia said to debut NV30 at Comdex Fall in November

http://www.digitimes.com/NewsShow/MailHome.asp?datePublish=2002/10/4&pages=04&seq=27

Nvidia has reportedly decided to officially introduce its top-end NV30 chip at the Comdex Fall exhibition, to be held in Las Vegas from November 18-22, after delaying the roll-out for months to change the design from a six-pipeline to eight-pipeline architecture.

So, if this is true, then the reason for the delay is that nVidia was blindsided by R300.....

 

[Randell]

The rumour that the NV30 went from 6 pipes to 8 pipes was promulgated before by Digitime I beleive. Most put no credence by it as all indications were that all DX9 parts were always 8 pipes. I dont know who can ever tell us for sure.

 

[alexsok]

That "6 pipelines" rumour originally came from Digitimes, so I wouldn't state that as a fact m8, although the possibility of that exists as well, but we can't take that as a fact, since from what I heard, the only reason NV30 is constantly delayed is because the 0.13-Micron process is still very immature...

edit:
oops, all the honor goes to Randell for bringing this up first...

 

[KimB]

I seriously, seriously doubt it could possibly be due to a change from 6->8 pipelines. First of all, have we yet seen a video card with a non-power-of-2 number of pixel pipelines (For the uninitiated, that means 1, 2, 4, 8, 16, etc.)? The answer is most obviously no because it's just more efficient in terms of computers to always do things in powers of two.

That, and as others have stated, major design changes just don't happen very late in development. It takes years to design a modern graphics chip architecture. The general design was probably finalized a long time ago (i.e. number of pipes, processing capabilities, etc.), with most of the recent work done in debugging and performance optimizations.

 

[Humus]

I don't think the non-power-of-two state of a 6 pipeline card would really matter in any measurable amount.

 

[arjan de lumens]

AFAIK, modern graphics cards tend to use framebuffer formats with a substantial amount of address swizzling/tiling, in order to keep memory bandwidth efficiently used. With a non-power of 2 pipelines, getting any kind of regularity to memory accesses in such a framebuffer will be rather difficult, so performance would suffer.

 

[Bigus Dickus]

First of all, have we yet seen a video card with a non-power-of-2 number of pixel pipelines (For the uninitiated, that means 1, 2, 4, 8, 16, etc.)? The answer is most obviously no because it's just more efficient in terms of computers to always do things in powers of two.

Original Radeon (R100) had three TMU's per pipe, and it's speculated that the NV30 may have three vertex shaders. Is that so much different?

But I agree with the general sentiment that the NV30 was likely always 8 pipelines... that's just a major change to make. Changing from a 128 bit to a 256 bit memory interface is more likely, but still a big freaking change that I don't think happened.

p.s. Randell: A DX9 card doesn't have to have 8 pipelines.

 

[Randell]

Bigus, yes I know e.g. Radeon 9500

I meant early info on 'known' DX( cards (R300, NV30, PVR Series 5) all indicated 8 pipes on each.

 

[Bigus Dickus]

Oh, my bad. Just the wording I guess... sounded like you thought a card had to have 8 pipelines to be DX9, not just that all rumored ones did/do.

Still... would be nice someday (in a few years perhaps?) to learn the true story of the NV30... it's about as complex and tangled as 3dfx's last projects.

 

[Randell]

np yes just the wording. ANd yes true story of NV30 and nVidia reaction to the R300 (i.e. did it catch them on the hop or is it just a shrug of the shoulders) and that would be linked to the X-Box and the delays in the Gf4 I'm sure

 

[Humus]

AFAIK, modern graphics cards tend to use framebuffer formats with a substantial amount of address swizzling/tiling, in order to keep memory bandwidth efficiently used. With a non-power of 2 pipelines, getting any kind of regularity to memory accesses in such a framebuffer will be rather difficult, so performance would suffer.

I don't see the connection between number of pipelines and memory access pattern. More pipelines means more accesses, no difference for power-of-two number of pipelines afaics.

 

[arjan de lumens]

With a power-of-2 number of pipelines, you can do one framebuffer access for all pipelines in parallel with a single power-of-2-bits width memory access. This simplifies design substantially. In the case of 6 pipelines in a 3x2 grid (or worse, 6x1) , the pixels won't lie in a single contiguous block in memory that can be addressed with a single aligned access (unless you either waste framebuffer memory or use a weird non-power-of-2-bits per pixel format). So you end up roughly doubling the number of framebuffer memory accesses over the case of 4 or 8 pipelines. I still don't see how this wouldn't hurt performance.

(BTW, this problem has no counterpart in the number of texture units per pipeline, which is why 3 units per pipeline as in Radeon 7500 works just fine.)

 

[Humus]

I was thinking mostly of texture accesses ... but anyway, the framebuffer generally is linear or tiled. In the linear case it's no problem getting linear writes with any number of pipelines. With a tiled framebuffer it's just a matter of finishing off a full tile into a tiny cache before writing to memory. The tile can have any dimensions.

 

[arjan de lumens]

OK. A 2x3 grid of pipelines would match a tile of dimensions 8x6 or 8x12 rather nicely. You still run the risk of getting a page break in the middle of a tile read-in or writeback, but the resulting performance hit is probably less than what I indicated before.

Still, redesigning to or from 6 pipelines sounds like a very large job. And designing for 6 pipelines sounds like an overall somewhat larger and more complex job than designing for 4 or 8 pipelines.

 

[Nagorak]

First of all, have we yet seen a video card with a non-power-of-2 number of pixel pipelines (For the uninitiated, that means 1, 2, 4, 8, 16, etc.)? The answer is most obviously no because it's just more efficient in terms of computers to always do things in powers of two.

Original Radeon (R100) had three TMU's per pipe, and it's speculated that the NV30 may have three vertex shaders. Is that so much different?

But I agree with the general sentiment that the NV30 was likely always 8 pipelines... that's just a major change to make. Changing from a 128 bit to a 256 bit memory interface is more likely, but still a big freaking change that I don't think happened.

p.s. Randell: A DX9 card doesn't have to have 8 pipelines.

TMUs and pixel pipes aren't the same thing.

The original Radeon had two pipes with 3 TMUs. Amazingly with its HSR and memory saving techniques the Radeon was more or less as fast as a brute force GF2 which had four pipes. With the Radeon 8500 ATi dropped the 3 TMUs, realizing that it hadn't really paid off with the original Radeon, but move to four pipes. GF3, GF4, etc all had four pipes with 2 TMUs. Now the R9700 has 8 pipes with 1 TMU. In all cases the pipe count is a factor of 2, which is the point being made. The TMU counts vary...but they're not the same thing...

 

[Bigus Dickus]

TMUs and pixel pipes aren't the same thing.

You're kidding, right? Obviously they're not the same thing, and a history lesson wasn't exactly necessary. My question was, to be a little less vague this time, does a non-power-of-two TMU arrangement or vertex shader number have any of the supposed complications that a non-power-of-two pixel pipe is claimed to?

Apparently, the answer is no.