I'll admit not to be perfectly sure what you mean here, because you aren't using the same (right?) terminology that I am...
G80: 8 clusters, 128 SPs, 32 TA/64 TF, 24 ROPs
G92: 8 clusters, 128 SPs, 64 TA/64 TF, 16 ROPs
D8P: 4 clusters, 096 SPs, 32 TA, 32 TF, 16 ROPs [what I was proposing]
Sorry, total brainfart I was thinking of 96 as 3/4 of 128 which is why I was talking in 3s and 4s
While you're proposing a 3:1 ratio I'd love to see 4:1 (hence 96x SPs + 24x SPs).
To be honest I suspect 3:1, it's a conservative change from G92. But I think it'd be 72x SPs + 24 TMUs - 3 clusters. Then, 3:1 makes a 192x SPs + 64x TMUs D9E come in at around 950M transistors, I reckon.
Shame the rumour says this chip is 64 SPs
The instant you introduce the possibility of a different ALU:TEX ratio, everything goes bananas
As for 55nm - I think you're overestimating the challenge this poses. The design rules are identical and unlike on 80nm, analogue & I/O is also scaled down by the same amount as digital circuitry. To give you an idea: back in June 2007, Jen-Hsun claimed during their analyst day they weren't yet sure whether their upcoming Hybrid SLI chipset would be on 65nm or on 55nm.
I reckon he was just bullshitting the analysts: give them something to get excited about (55nm, wow - Hybrid, groovy) to paper over the fact that NVidia was making (and has made) a right mess of chipsets in 2007.
Plus, NVidia delivered its first 90nm chipsets a year before its first 90nm GPU - though to be fair G71 was prolly several months late.
Finally, you're missing the crux of what I'm saying. That D9x is late, and, that a February 55nm D9x would have to be on the
same schedule as ATI's RV670 (which was due for January but bizarrely was 2 months early). NVidia has deliberately lagged ATI on GPU processes for years now. Even if it's only 4-6 months.
We're still getting used to the fact that 55nm GPUs are out there when the first 65nm GPUs only hit in July (though they should have arrived in March or perhaps earlier, to be fair).
If you said that the delays to this chip (which I reckon should have been launched in November, alongside D9E) have given NVidia the opportunity to re-target to 55nm, then I might have some sympathy. 65nm has clearly given a lot of trouble at TSMC this year, but it appears that 55nm didn't get pushed back, making 55nm look like a faster transition than it really was.
Does anyone remember the very first rumours of a 65nm RV670 which was 3/4th R600 in late Q3?
Planted by ATI? It sure worked.
Calling this GPU D9P appears to be more of the same misinformation (except the other way round), when it's priced/positioned to be D9M. Hell, remember that 8600GTS was $200+ when it launched and this is destined for $150.
If this is D9
P then D9
E will be awful, being only about 33% faster. D9E as configured earlier in this post, should be 2x the performance of this chip: 192 v 96 SPs (or 72) and 64 v 32 (or 24) TMUs.
Damn, this is so random. My main interest in posting in this thread is that calling a $150 part D9
P is ridiculous.
Jawed