Panajev2001a
Veteran
I think they can make it work: the problem might be make it slow enough .
Imagine a dual channel solution, with 2 DRAM modules per channel and providing 64 bits for the data bus ( 128 pins ).
If they change the clock ( the driver could do it ) from 400 MHz ( that produces a 3.2 GHz signalling rate ) to 100 MHz we would have a signalling rate of 100 * 4 = 400... 400 * 2 = 800 MHz.
Now, disable one of the two channels and you end up with a 32 bits bus with an effective data signalling rate of 800 MHz.
800 MHz * 4 bytes/clock = 3.2 GB/s.
To tell you the truth, XDR would still be a little faster in the worst case scenarios of Direct RAMBUS as it does not multiplex the data and address busses, but has two separate paths. Also each DRAM module would have two 8 bits bi-directional busses thus enabling parallel LOADs and WRITEs.
Imagine a dual channel solution, with 2 DRAM modules per channel and providing 64 bits for the data bus ( 128 pins ).
If they change the clock ( the driver could do it ) from 400 MHz ( that produces a 3.2 GHz signalling rate ) to 100 MHz we would have a signalling rate of 100 * 4 = 400... 400 * 2 = 800 MHz.
Now, disable one of the two channels and you end up with a 32 bits bus with an effective data signalling rate of 800 MHz.
800 MHz * 4 bytes/clock = 3.2 GB/s.
To tell you the truth, XDR would still be a little faster in the worst case scenarios of Direct RAMBUS as it does not multiplex the data and address busses, but has two separate paths. Also each DRAM module would have two 8 bits bi-directional busses thus enabling parallel LOADs and WRITEs.