ATI Licenses Tensilica's Xtensa Configurable Processor
- Thread starter Dave Baumann
- Start date
Well, I don't see where something as ambitiously flexible as that would fit for desktop motherboards, at least with where I expect Windows to take things.
I could see some possibilities for expanded AIW functionality while maintaining competitive adaptibility (codec evolutions and after-market software development), and implementing similar in notebooks, but that still seems a bit nebulous.
The best fit I can see what it looks being aimed for is set top and possibly hand held solutions.
It seems tailor made, for reasons along the lines I listed for the AIW solution, for providing robust and "evolvable" solutions for DTV, cable, etc. Perhaps also solutions more completely provided by ATI (in terms of development tools and all hardware components) if this isn't the case already.
As far as handhelds, this would depend on power usage efficiency, which seems to be something the company considers a viable strength of their design. I haven't seen the evidence of the software/OS side of being able to capitalize on such flexibility yet, though it seems where things could be heading.
...
There is also the probably rather wild (AFAIK) possibility that some of the design elements of the xtensa implementation programmability would be beneficial to GPU design (more likely if this is an "after the fact" announcement), but the wording doesn't seem to lend itself to that AFAICS (and the above theories seem to make sufficient sense without depending on drastic unknowns).
I could see some possibilities for expanded AIW functionality while maintaining competitive adaptibility (codec evolutions and after-market software development), and implementing similar in notebooks, but that still seems a bit nebulous.
The best fit I can see what it looks being aimed for is set top and possibly hand held solutions.
It seems tailor made, for reasons along the lines I listed for the AIW solution, for providing robust and "evolvable" solutions for DTV, cable, etc. Perhaps also solutions more completely provided by ATI (in terms of development tools and all hardware components) if this isn't the case already.
As far as handhelds, this would depend on power usage efficiency, which seems to be something the company considers a viable strength of their design. I haven't seen the evidence of the software/OS side of being able to capitalize on such flexibility yet, though it seems where things could be heading.
...
There is also the probably rather wild (AFAIK) possibility that some of the design elements of the xtensa implementation programmability would be beneficial to GPU design (more likely if this is an "after the fact" announcement), but the wording doesn't seem to lend itself to that AFAICS (and the above theories seem to make sufficient sense without depending on drastic unknowns).
A tablet window device for under $100.... 
Perhaps to power an Audio processing subsystem on a motherboard/console/settop?
Edit: Hrm... it isn't entirely clear to me from the press release just what they licensed. I'm guessing what they licensed was the XtensaLX IP, and if thats the case, being that Xtensa also offers an audio engine that would suggest that the license isn't for audio purposes.
Edit: Hrm... it isn't entirely clear to me from the press release just what they licensed. I'm guessing what they licensed was the XtensaLX IP, and if thats the case, being that Xtensa also offers an audio engine that would suggest that the license isn't for audio purposes.
IIRC ATI is only providing the graphics / UMA for XBox2, I believe it was SiS that's providing the MCP.
DaveBaumann said:OK, what do we think this is all about then? What application - phone/handheld, desktop/notebook, console or all of the above?
I skipped through the PDF from Microprocessor Forum at their website. It sounds like technology a company like SiliconHive is selling as well. A highly optimized VLIW processor with smart compiler technology.
I think it's the future for (embedded) consumer applications. Think about something like a portable video player (e.g. Microsoft's PMC). Using a DSP allows you to runs all kinds of codecs on the same piece of silicon. It's small, takes not a lot of power and is flexible.
Unknown Soldier
Veteran
Would this maybe be an issue?
Software/firmware developers, run your C code faster - no changes required.
Wouldn't this mean maybe a more efficient way for ATI GPU's to process C code. Most games are written in C code .. right??
US
Software/firmware developers, run your C code faster - no changes required.
Wouldn't this mean maybe a more efficient way for ATI GPU's to process C code. Most games are written in C code .. right??
US
Aha! Something I can actually comment on in the 3d technology forum!
Oh happy day!
The tensilica processor is essentially a modern RISC processor that is pretty typical RISC.
It can have a DSP add-on that includes the typical DSP functions: automodulo addressing, address wrap around, bit reverse addressing for FFTs, single cycle MAC, etc.
In many ways it's equivalent to the latest ARM processor. I think the Xtensa is a little more modern and built from scratch, rather than the ARMs evolutionary growth from the original ARM1, however.
The real mojo of Tensilica is their ASIC development environment. They have a way of having the ASIC designer be able to build custom instructions that are fully pipelined and integrated into the ALU, covered by test vectors, and supported by the compiler as intrinsics by just writing some pseudocode. These instructions can operate on as many registers as it wants (and you can feed data into a pipeline, etc), and the instruction itself can have internal state, etc.
Tensilica bills the processor as the "Application specific processor". The idea is to write the application and/or algorithm, profile it, then optimize the hot spots and replace that algorithm with their ASIC instruction.
While it claims to be reconfigurable, its reconfigurable only in the sense that the tensilica core is reconfigurable, but the ASIC designers core isn't. When the ASIC designer is happy with their design (including extension instructions), they press the 'make me a processor button' and tensilica gives them back a core thats written in stone (or silicon)
It works wonders for bit manipulative algorithms like jpeg encode/decode, or bitstuffing, etc. They clean up on the EEMBC test suite for full on optimization because they can take all sorts of complex bit manipulations and condense it down to a single instruction.
HOWEVER, from my limited knowledge of fragment processing, such a thing wouldn't be the shiznit for such tasks, as the processor is too big for such a task, and isn't parallelized enough, nor VLSI enough.
So, my vote is "no use in a graphics add in chip"
Next, does it have use in a hand held/PDA product? Seeing the "vast" array of processors used in the PDA arena, my vote is no. PocketPC has settled on ARM as the processor of choice, and Xtensa isn't ARM, so you'd have to recompile all the applications, etc. Its the same reason you don't see MIPs or SH-x based pocketPCs: the platform has been standardized.
MCP replacement? I dunno. Its possible, though I question why you'd go that distance when there's other DSPs out there for the purpose of encoding multichannel audio into AC-3.
Next, set top box. Here's where my spidey senses tingle. Currently they (ATI) have a MIPS based product used in the RokuLabs HD1000 (among others) set top box. MIPS is expensive, and doesn't offer the same flexibility and customizability as Tensilica. This would be perfect for accellerating MPEG-4 video, etc, yet still offer a normal processor for running an OS and filesystem on. It doesn't need to be a standard platform, since its not fitting into some microsoft dictated paradigm.
Anyways, thats my take on it.
Oh happy day!
The tensilica processor is essentially a modern RISC processor that is pretty typical RISC.
It can have a DSP add-on that includes the typical DSP functions: automodulo addressing, address wrap around, bit reverse addressing for FFTs, single cycle MAC, etc.
In many ways it's equivalent to the latest ARM processor. I think the Xtensa is a little more modern and built from scratch, rather than the ARMs evolutionary growth from the original ARM1, however.
The real mojo of Tensilica is their ASIC development environment. They have a way of having the ASIC designer be able to build custom instructions that are fully pipelined and integrated into the ALU, covered by test vectors, and supported by the compiler as intrinsics by just writing some pseudocode. These instructions can operate on as many registers as it wants (and you can feed data into a pipeline, etc), and the instruction itself can have internal state, etc.
Tensilica bills the processor as the "Application specific processor". The idea is to write the application and/or algorithm, profile it, then optimize the hot spots and replace that algorithm with their ASIC instruction.
While it claims to be reconfigurable, its reconfigurable only in the sense that the tensilica core is reconfigurable, but the ASIC designers core isn't. When the ASIC designer is happy with their design (including extension instructions), they press the 'make me a processor button' and tensilica gives them back a core thats written in stone (or silicon)
It works wonders for bit manipulative algorithms like jpeg encode/decode, or bitstuffing, etc. They clean up on the EEMBC test suite for full on optimization because they can take all sorts of complex bit manipulations and condense it down to a single instruction.
HOWEVER, from my limited knowledge of fragment processing, such a thing wouldn't be the shiznit for such tasks, as the processor is too big for such a task, and isn't parallelized enough, nor VLSI enough.
So, my vote is "no use in a graphics add in chip"
Next, does it have use in a hand held/PDA product? Seeing the "vast" array of processors used in the PDA arena, my vote is no. PocketPC has settled on ARM as the processor of choice, and Xtensa isn't ARM, so you'd have to recompile all the applications, etc. Its the same reason you don't see MIPs or SH-x based pocketPCs: the platform has been standardized.
MCP replacement? I dunno. Its possible, though I question why you'd go that distance when there's other DSPs out there for the purpose of encoding multichannel audio into AC-3.
Next, set top box. Here's where my spidey senses tingle. Currently they (ATI) have a MIPS based product used in the RokuLabs HD1000 (among others) set top box. MIPS is expensive, and doesn't offer the same flexibility and customizability as Tensilica. This would be perfect for accellerating MPEG-4 video, etc, yet still offer a normal processor for running an OS and filesystem on. It doesn't need to be a standard platform, since its not fitting into some microsoft dictated paradigm.
Anyways, thats my take on it.
Though, looking at the LX processor (which wasn't available when we evaluated their technology), it does have aspects that may be applicable to fragment shading.
So, I'll leave that open, as well, though I do question if thats the right engine to be scheduling stuff optimally for high end graphics.
EDIT: looking deeper, the queues (http://www.tensilica.com/html/ports_and_queues.html) seem to be a perfect match for DirectX's stream based processing paradigm, though I'm not sure how you'd modify the operator used by the queue, given what I know about how TIE works. Maybe a bunch of TIE to do all the different operations?
As the brain cogitates, I wonder if the idea isn't to reproduce the Sm3.0 instruction set with TIE, and use these queues to parallelize the operations x4 or x8 (or whatever).
Oh well, I'm sure somebody at ATI is snickering at me.
So, I'll leave that open, as well, though I do question if thats the right engine to be scheduling stuff optimally for high end graphics.
EDIT: looking deeper, the queues (http://www.tensilica.com/html/ports_and_queues.html) seem to be a perfect match for DirectX's stream based processing paradigm, though I'm not sure how you'd modify the operator used by the queue, given what I know about how TIE works. Maybe a bunch of TIE to do all the different operations?
As the brain cogitates, I wonder if the idea isn't to reproduce the Sm3.0 instruction set with TIE, and use these queues to parallelize the operations x4 or x8 (or whatever).
Oh well, I'm sure somebody at ATI is snickering at me.
Maybe this sort of extension to the system from Tensilica would work:
http://www.stretchinc.com/products_overview.php
They have "replaced" the ASIC with an FPGA (or something close) called ISEF and so the processor is now reconfigurable on the fly. Maybe even the tools from Tensilica could be used cause their system is based on the Tensilica-CPU too.
[dream-mode]
Maybe we will see an future implementation with CPU+ISEF+software which adapt's itself to the running C/C++ program on the fly.
[/dream-mode]
asicnewbie
Newcomer
The US Logic HDTV set-top-box (http://www.usdigitalhdtv.com) also uses ATI's Xilleon chipset. The same box is also available in 'subscription' form (http://www.usdtv.com), which is simply a different firmware-personality.RussSchultz said:
From what I'm told, dedicated (standard-cell ASIC) silicon is still the method of choice for implementing the brute pixel-pushing work in standard video-codecs (i.e. standard = frozen, unchanging syntax.) MPEG-4 (not AVC) has been around long enough that I'd expect ATI to already have a fixed-function decoder in the works. It's unlikely a configurable CPU-core, with no outside hardware-acceleration, could outperform a fixed-function or hybrid/CPU+pixel-engine decoder -- at least not in terms of area or speed ... well perhaps "time to market."
Its quite possible the Tensilica is deployed as a microcontroller within the MPEG-4 decoder. I.e., the CPU handles error-trapping, stream demultiplexing, video-bitstream parsing and variable-length code unpacking. Error-trapping is a sparse operation that benefits from the intelligence of a CPU. Bitstream-parsing and VLC is computationally "irregular" (i.e. it's all about crunching irregularly bit-sized codewords), yet low-bandwidth -- below 20Mbits/sec. These attributes are suitable for a general-purpose CPU, though a CPU + custom-instructions can do it more efficiently.
I tend to agree. Although I'd look at the Tensilica more as the "manager" overseeing a bunch of fixed-function, sub-ordinate pixel-pushing blocks (iDCT-transform, motion-comp blocks, and deinterlacing pixies.) The manager is just there to do paperwork and feed its subordinates to keep them busy.
I've heard ARM is even more expensive than MIPs (due to ARM's de-facto dominance in the embedded market.) But I wonder, in terms of licensing costs, was Tensilica really the cheapest?
It can be. Tensilica only charges for a processor once (though you have to pay again if you change the custom instructions), plus royalties. ARM has a re-use fee, plus royalties. I'm not sure about MIPS, since we rejected them for technical reasons (size and power).asicnewbie said:
Tensilica is pretty cheap NRE-wise.
My guess is either microcontroller for some subsytem or possibly audio. The instruction set is too non-standard to be used as the "main" processor for anything. And as long as your instruction extensions fit into the usual ALU-style, TIE works out ok.
For audio though I thought the RISC style made it pretty awkward as a DSP. Same as every other RISC core that attempted DSP extensions. I suppose if you buy their canned audio solutions you don't have to deal with this awkwardness yourself.
My guess is either microcontroller for some subsytem or possibly audio. The instruction set is too non-standard to be used as the "main" processor for anything. And as long as your instruction extensions fit into the usual ALU-style, TIE works out ok.
For audio though I thought the RISC style made it pretty awkward as a DSP. Same as every other RISC core that attempted DSP extensions. I suppose if you buy their canned audio solutions you don't have to deal with this awkwardness yourself.
