ARM announces new Cortex A72 core

[Ailuros]

Last OT post wrt to Mali and FLOPS the best response comes from ARm itself, real world evidences seems to corroborate theirs claims:
http://community.arm.com/groups/arm...ops--how-arm-measures-gpu-compute-performance

As useful as any marketing blog out there. The T760MP8 at a turbo frequency of 772MHz in the Exynos7420 (being the biggest Midgaard integrated to date I'm aware of) comes to 198 GFLOPs FP32 as a peak theoretical and 6.18 GTexels/s fillrate (1TMU/cluster); what is left then in real time is another chapter, but it doesn't change one bit my quote above from several months ago.

Up to T7xx Midgaard cores are capable of 32 FLOPs/clock FP32 and if you'd want to also count SFU ops then 34/clock. The part in the above blog writeup where they mention that they don't "count" SFU FLOPs is probably the joke of the day. I recall them counting them first into the peak FLOP count with their T604.

 

[liolio]

A >5 months delay for an answer and a quite long post just to actually agree with the quoted content of a few sentences is quite an art I must admit

we disagree I will take Anandtech estimates over yours any days sorry.
As for your other post, I don't really care what you think, it seems that you like big number of cores or FLOPS for their own sake without much interest to how that relates to the really world performance. I was not really discussing with you more thinking (/writing) out aloud I'm sure done discussing with you now.

 

[Xmas]

Up to T7xx Midgaard cores are capable of 32 FLOPs/clock FP32 and if you'd want to also count SFU ops then 34/clock. The part in the above blog writeup where they mention that they don't "count" SFU FLOPs is probably the joke of the day. I recall them counting them first into the peak FLOP count with their T604.

Scalar MUL, scalar ADD, vector MUL, vector ADD, vector dot product. That's 17 FLOPs per ALU pipeline, all multiplication or addition.

 

[Ailuros]

we disagree I will take Anandtech estimates over yours any days sorry.
As for your other post, I don't really care what you think, it seems that you like big number of cores or FLOPS for their own sake without much interest to how that relates to the really world performance. I was not really discussing with you more thinking (/writing) out aloud I'm sure done discussing with you now.

Νowhere did Anandtech state anything different. How each sterile FLOP count relates to real time performance can easily be cross-referenced with public benchmark results especially from Anandtech's relevant reviews. As for the rest, it's common practice that others reply to your posts whether we like it or not.

 

[Ailuros]

Scalar MUL, scalar ADD, vector MUL, vector ADD, vector dot product. That's 17 FLOPs per ALU pipeline, all multiplication or addition.

http://www.anandtech.com/show/8234/arms-mali-midgard-architecture-explored/5

The vector and scalar operations are relatively self-explanatory, while the dot products are a result of using the vector special functions unit. To that end every architecture possesses SFUs in some form to handle dot products, transcendentals, and other complex operations, but their inclusion in FLOPS counting is uncommon. Most architectures merely count FLOPS as adds and multiplies through the ubiquitous and all important MAD (Multiply-Add) instruction.

In the end whether 32 or 34 FLOPs/cluster it doesn't change much for the above. Irrelevant of which maximum design latency each GPU IP has, it is NOT realistic to expect today more than 8 clusters from an architecture like Midgaard in a smartphone SoC. That's all it was about.

 

[Xmas]

In the end whether 32 or 34 FLOPs/cluster it doesn't change much for the above.

If you don't count the dot product it's 10 FLOPs per ALU pipeline. But if you're not counting dot products you might as well not count sum-of-products (two-component dot product) like some architectures. Or discount MADs. After all, separate MUL and ADD units are more flexible, provided you can feed them.

 

[fxtech]

3.0 ghz via http://www.gizchina.com/2015/07/09/mstars-high-end-s700-pro-to-be-unveiled-in-october/

The Mstar S700’s CNC zinc alloy chassis clearly takes it’s inspiration from the Oppo R7, though that isn’t such a bad thing when you get down to it. The Mstar S700 Pro will possibly be one of the first phones to carry Qualcomm’s brand new Snapdragon 820, a 64-bit quad core processor clocked at 3.0GHz coupled with the Adreno 530 GPU (It’s also a mobile stove). Other specs include 4/32GB of RAM/ROM, a 5.5-inch QHD display protected by 2.5D Gorilla Glass 3, expandable memory up to 128GB, a 3500mAh battery and an Ultrasonic Sense fingerprint sensor, something new that comes with the new Snapdragon 820