We have just released version 2 of DESTINY, which can model:
* (2D/3D) SRAM and eDRAM
* (2D/3D, SLC/MLC) STT-RAM, ReRAM and PCM
* (2D, SLC/MLC) SOT-RAM, Flash, DWM
SLC/MLC = single/multi-level cell, DWM = domain wall memory (aka racetrack memory), SOT-RAM = spin orbit torque RAM, STTRAM = spin transfer torque RAM, PCM = phase change memory, ReRAM = resistive memory (also called RRAM)
Features of DESTINY:
* Can model 22nm to 180nm technology nodes
* It can model both conventional and emerging memories
* Validated against several commercial prototypes
In its purpose, DESTINY is similar to CACTI, CACTI-3DD or NVSim. The source code is available here: https://bitbucket.org/sparsh_mittal/destiny_v2
The journal paper which described DESTINY in full details is available here: https://www.academia.edu/34545611/D...d_Multi-Level_Cell_Memory_Modeling_Capability
* (2D/3D) SRAM and eDRAM
* (2D/3D, SLC/MLC) STT-RAM, ReRAM and PCM
* (2D, SLC/MLC) SOT-RAM, Flash, DWM
SLC/MLC = single/multi-level cell, DWM = domain wall memory (aka racetrack memory), SOT-RAM = spin orbit torque RAM, STTRAM = spin transfer torque RAM, PCM = phase change memory, ReRAM = resistive memory (also called RRAM)
Features of DESTINY:
* Can model 22nm to 180nm technology nodes
* It can model both conventional and emerging memories
* Validated against several commercial prototypes
In its purpose, DESTINY is similar to CACTI, CACTI-3DD or NVSim. The source code is available here: https://bitbucket.org/sparsh_mittal/destiny_v2
The journal paper which described DESTINY in full details is available here: https://www.academia.edu/34545611/D...d_Multi-Level_Cell_Memory_Modeling_Capability
