AMD needs to use the same cache design. (SOI was blamed for Barcelona's L3 density, and it hasn't improved for Shanghai).The L3 array is where more work can be done, as for now AMD is just recycling the L2 SRAM design for the L3.
AMD is working on a new CPU architecture codenamed 'Bulldozer'. Derivatives include monolithic 8-core and 12-core processors. The 12-core processor is now codenamed Magny-Cours, the 8-core part is called Sao Paulo. These processors could feature four parallel HyperTransport 3.0 interconnects, upto 12 MB of L3 cache and 512 KB L2 cache per core. It's known that AMD could be working on quad-channel DDR3 (both registered DDR3 under G3MX and unregistered). Socket G34 seems to have 1,974 pins.
I wonder how will a 12 core Magny-Cours stack up against a 32 core Larrabee
One step closer to slot-A?
Why would it? Larrabee is a graphics product that just so happens to be GPGPU (and x86) capable. Single-thread performance will be *attrocious* compared to even current x86 processors, let alone what's to come at the time of Larrabee's release.
Why would I want to compare single-threaded performance? You would think I am talking about those x86 GPGPU programs. And no I think larrabee is more like a general purpose processing unit just happens to have graphics functionalities attached to it.
Show me the apps, then we'll talk perf.