demalion said:
XGI said:
If you understand anything about wafer process, then you will know that yield rate is die size depedant! Although that every foundary claim that they have such and such yield rate but the truth is... that only applies to very small dies.
...
If you have a dual chip design, then it will result in more gross die and also very importantly higher yield! With a bigger chip single design: it result in smaller gross die * lower yieldrate!
I don't know, it doesn't seem to say anything about a larger process to me (here, or the other bits I didn't quote), but I could somewhat imagine how someone might read that into these particular parts.
It implies a larger process to me. This is just a restatement of Moore's Law: the transistor count at which it becomes economical (balancing costs due to poor yields at the high transistor count extreme, vs. a base marginal cost due to packaging and testing costs at the low transistor count extreme) to integrate what was formerly two IC's into one IC rises at an exponential rate w.r.t. time (which is a proxy for process improvements).
Not sure if that sentence made any sense (but if anyone can figure it out, I expect you to
), so I'll try to restate it: Moore's Law is a statement about the point at which it becomes cheaper to combine your functionality into one chip instead of splitting it up among two (or more) chips. In particular, that crossover point (measured in transistor count) rises exponentially with time, which is another way of saying it rises exponentially with process improvements, and that process improvements tend to be roughly linearly spaced in time.
Anyways, any time it is cheaper to do something with two chips than with one, eventually (after a certain number of process shrinks) it will be cheaper to fit it on one chip instead of two. This is the logic behind the microprocessor; the integrated chipset; cell phones that surf the web, take pictures, play games and playback sound and video; SoCs; and so on.
XGI proposes to use two chips (at some unknown manufacturing process) to achieve what would appear to be a bit less functionality than what the .15u R300/R350 achieves with one. Part of the reason for this is that they except to sell many more one-chip versions of their card, and this way they can get two products for the ASIC-level engineering cost of one (although now there are extra board-level engineering costs). But part of the reason is clearly because they think it will be cheaper (or at least competitive) in terms of marginal manufacturing cost. This strongly suggests the chips are .15 and not .13.
Perhaps the chip is targeted .15 and not .13 because TSMC is indeed giving them a better deal at that process. Perhaps because the product was supposed to launch earlier--when .15 would have made more sense--but was delayed. Perhaps because XGI's engineers were more comfortable working with .15 and avoiding any tricks or difficulties that may exist at .13. Or perhaps because the yield curve at .13 is such that for a small enough chip it really is still cheaper to use .15.
In any case, the choice doesn't seem particularly forward looking. .15 may still be somewhat cheaper in the short-term, but as yields improve using .13 should easily lead to lower costs in the long-term. It doesn't seem like the right choice for a design that's meant to stick around for very long.