Nvidia GT300 core: Speculation

[CarstenS]

Given that AMD has been intentionally veiling their DX11 parts' performance in every DX11 test so far, would it be very surprising if currently available drivers would not run the cards to their fullest potential?

 

[MfA]

I'm willing to give GT3xx a bit of breathing room as well if its going up against an AFR solution from AMD. Either a modest price premium, a small performance disadvantage or even a small combination of both would be acceptable to me if it means no input lag and more consistent performance.

This would probably be better for us the consumers. As much as I'd like AMD to master cheap MCMs with massive sideports it wouldn't be good for competition at the moment.

 

[Jawed]

As much as I'd like AMD to master cheap MCMs with massive sideports it wouldn't be good for competition at the moment.

You've said this before. Why?

Jawed

 

[MfA]

You've said this before. Why?

Because NVIDIA is months behind the curve, without an architectural advantage in at least one consumer segment they would be in for major hurt in margins IMO. I don't think scientific computing alone is going to bring in the bread.

 

[Jawed]

Well I think rumours of NVidia's laggardliness are greatly exaggerated. I wouldn't be surprised if NVidia shows GT300 running on W7 launch day - it's technically possible given the tape-out in July. That'll chasten AMD's lead, even if demand might make it hard to buy one for another month or two.

Jawed

 

[digitalwanderer]

even if demand might make it hard to buy one for another month or two.

They'd have to pretty much go with the A1 was to pull that off, wouldn't they?

 

[Jawed]

Dunno, if it's A1 - I'm doubtful that was the first tape-out in July. Regardless, it depends how desperate NVidia is to have a spoiler on the market, like GTX295 or 7800GTX, and a halo gets extra shine when you can say "we can't keep up with the demand!".

Jawed

 

[digitalwanderer]

Speak of the devil and someone posts a story about it!

NVIDIA KEEPS HOWLING that it will have GT300 out this year, so we did a little digging on the topic. All you can say is that it seems willing to fritter away large swaths of its and TSMC's cash to meet a PR goal.

The short story is that GT300 taped out in week 3 or 4 of July 2009. It is a huge chip, about 23mm X 23mm, but we are now hearing it will be 23.something X 23.something millemeters, so 530mm^2 might be a slight underestimate. In any case, TSMC runs about 8 weeks for hot lots, 2 more weeks for bringup, debug, and new masks, and finally another 10-12 for production silicon.

GT300 wafers went in at TSMC on August 3, give or take a couple of days, so if you add 22 (8 + 2 + 12) weeks to that, you are basically into 2010 before TSMC gives you the wafers back with pretty pictures inscribed on them. Like babies, you just can't rush the process with more, um, hands.

While it is not rushable, you can do some of it in parallel, and that uses what are called risk wafers. Those wafers are put in at the same time the first silicon hot lots are, so they have been in the oven about 2 weeks now. Just before the final layers are put on, the risk wafers are parked, unfinished, off to the side of the TSMC line.

The idea is that with the hot lots, Nvidia gets cards back and debugs them. Any changes that are necessary can hopefully be retrofitted to the risk wafers, and then they are finalized. Basically, the risk wafers are a bet that there won't be anything major wrong with the GT300 design, in that any changes are minor enough to be literally patched over.

Risk wafers are called risk wafers for a reason. If you do need to make a change big enough, say a metal layer spin, the risk wafers are then what are called scrap wafers. You need to make damn sure your design is perfect, or nearly perfect, before you risk it. Given Nvidia's abysmal execution recently, that is one gutsy move.

If Charlie is right, I'd say it's not "gutsy" so much as "insanity driven by desperation"!

 

[Domell]

1. GDDR5 memory

2.use 512-bit memory bus

3. To provide 280 GB / sec bandwidth of about (higher than RV870)

4. GM is now calculated to be 2.2 times higher than the GT200

5.1700MHz frequency shader

Bold guess 6.die size

Here is source.

http://translate.google.com/transla...orum-206-1.html&sl=zh-CN&tl=en&hl=en&ie=UTF-8

From Xtremesystems Forum. Some info about GT300. I wonder if true.

 

[silent_guy]

If Charlie is right, I'd say it's not "gutsy" so much as "insanity driven by desperation"!

He claims that a metal spin will result in scrapping the whole risk lot. It's just the opposite: the reason you park the wafers unfinished is because it allows you to do a metal spin later on without having to scrap them. Since the vast majority of bugs are fixable in metal only, you get the best of both worlds: the chance to make a quick fix that's less costly (because base is more expensive than metal) and a way to reduce the fab delay significantly (because base processing take roughly half of the processing time through the fab.) There is not a single company who doesn't park wafers before metal for exactly this reason.

The beauty of this article is not in the actual information content but in the way it shows directly how the emperor has no clothes.

 

[dizietsma]

Dunno, if it's A1 - I'm doubtful that was the first tape-out in July. Regardless, it depends how desperate NVidia is to have a spoiler on the market, like GTX295 or 7800GTX, and a halo gets extra shine when you can say "we can't keep up with the demand!".

Jawed

Well history has proven that the person who releases first has the advantage of course and with a big improvement might well think "that's good enough for me" and put down the $ rather than wait for details from the other company. I'm thinking R300 here and also G70. When competing cards were released close together such as nv40 and X800 then that temptation is not there.

So I would guess nvidia will show "it is worth waiting for" if they can. Of course that also depends on the extra length of waiting period and how far they are head performance wise.

Personally I am going for a card this time and if ATi have cards available October and there is no information on nvidia and it is likely to be December -Feb sometime then I will probably jump for an ATi as that will be good enough for me.

EDIT ... oops I meant G80

 

[Ailuros]

The beauty of this article is not in the actual information content but in the way it shows directly how the emperor has no clothes.

*runs to fetch a container full of talk*

 

[Arun]

I have been saying they were doing exactly that ever since Charlie claimed it was impossible for them to meet their 2009 target (feel free to dig up the forum posts if you don't believe me) - so it's good to see he's finally hedging his bets. Of course, even I knew what silent_guy just explained The only other place where I can see more risk being taken is in terms of PCBs, but I'd assume the standard procedure already stockpiles them in advance?

The rest of Charlie's article also has some bizarre assertions. "TSMC [...] is charging Nvidia per good chip while yields are below 60%" - uhm, doesn't he realize good chip-based pricing is standard procedure for a new process, and it obviously takes die size and other factors into account? It's mostly just a way for the foundry to take the loss if yields aren't improving fast enough while making sure customers are willing to ramp on a new process. And before that he said "we hear Nvidia is paying a premium for each of the risk wafers" - so is it per wafer or per good die after all? Unless risk refers strictly to hot lots, which would contradict the rest of the article? And why would I believe they're being charged a premium when NV themselves claimed to have preferential pricing and Jen-Hsun and Morris Chang have been good personal friends for a very long time? This is patently absurd.

As for Charlie's obsession with Global Foundries - here's a hint: it won't matter a single discrete GPU product coming out at either NVIDIA or AMD for a full *two* years. 32G is dead and both GF and TSMC are now claimed 28HP tape-outs will happen in 4Q10 - y'know, like 40nm tape-outs apparently happened in 4Q08?

 

[Jawed]

Woah, so NVidia's going to try to produce say 600,000 GT300s (say TSMC guarantees 60% yield) between now and Christmas. Awesome, they're going to make TSMC pay! Wow, TSMC must be desperate. (Sure, NVidia will then have to bin those GPUs and maybe only 80% of those will work as GTXs and GTSs.)

GT216 is A2, which is one metal spin it seems. So by cherry-picking from the first lot (50 wafers?), NVidia can get a few hundred review samples out for W7 launch on A1. Then worry about successive metal spins to fix up the remaining risk production (thousands of wafers) so that they have enough to sell.

It really does sound like 7800GTX-512 all over again, in terms of grabbing the limelight - or like GTX295 in terms of pretending that it's a hard launch. Back when 7800GTX-512 happened ATI made the mistake of not having R580 ready to go (it was 10 weeks later). Wonder if AMD will make the same mistake this time?

Jawed

 

[Jawed]

I'm curious whether there's any room to be even more aggressive though. Obviously you could mass produce a few hundred wafers on A1 all the way to the last stages and hope for the best... But is there any intermediate step? I guess what Charlie would be describing, if it made any sense (but I suspect it doesn't) is a scheme where you went through most metal layers but not all. I can't see what the point of that would be in practice though.

silent guy seems to be saying that wafers are parked before the majority of metal layers are constructed.

Really the question is about the meaning of "metal spin", what kind of faults you can fix. But what's the ordering of metals?

From what I can gather, the top of the chip is bumps and vias into a few layers of power redistribution, along with signals. I don't know how many layers that is, 3,4? Then there's logic. Then, presumably cell connectivity (e.g. inter-transistor connections to make a memory cell). Then localised connectivity (e.g. a pipeline), then funtional connectivity (e.g. instruction decoder) and then inter-function connectivity (e.g. L2->L1 data bus).

Are there more layers of power distribution, below logic?

Jawed

 

[Florin]

I have been saying they were doing exactly that ever since Charlie claimed it was impossible for them to meet their 2009 target (feel free to dig up the forum posts if you don't believe me) - so it's good to see he's finally hedging his bets.

Looks more like all bets are off

Which way will it go? We will know in Q1. There will either be an updated spec card with a higher stepping or there won't be. Nvidia will have cards out in real, not PR, quantities or it won't. Nvidia will either have a hidden charge on its balance sheet or TSMC will.

Here's another prediction; Whatever happens, Charlie will manage to find a negative spin on it. Nvidia will end up being late? Well, they're just dumbasses. Nvidia not late? Desperate dumbasses.

 

[Arun]

Woah, so NVidia's going to try to produce say 600,000 GT300s (say TSMC guarantees 60% yield) between now and Christmas. Awesome, they're going to make TSMC pay! Wow, TSMC must be desperate. (Sure, NVidia will then have to bin those GPUs and maybe only 80% of those will work as GTXs and GTSs.)

As I said above, let's not be ridiculous. This is perfectly standard procedure. NVIDIA is *already* paying for GT21x per good chip and Morris Chang has explicitly said 40nm gross margins weren't as high as 65nm right now but they should improve to the same level as yields improve in the next few months. Selling per good chip doesn't require a "write-off" as Charlie claims, it's just standard gross margin accounting. And TSMC doesn't take the design risk if A2 doesn't work out because of design bugs, obviously.

GT216 is A2, which is one metal spin it seems. So by cherry-picking from the first lot (50 wafers?), NVidia can get a few hundred review samples out for W7 launch on A1. Then worry about successive metal spins to fix up the remaining risk production (thousands of wafers) so that they have enough to sell.

That's assuming A1 is sufficiently bug-free to go to reviewers. That's a big assumption. The fact of the matter is that if they're willing to pay a bit extra every step of the way and take a bit extra risk, they can easily hard launch this thing in late November.

Here's the part where they are IMO likely to take extra risks to save time: instead of waiting for an A2 hot lot to be back from the fab and fully tested/debugged, they will probably send their entire production lot to be finished with the A2 metal layers before having actually tested that respin. The hot lots from that batch (which, remember,were normal lots for the silicon layer) are the review samples; the normal lots are the retail chips.

By the time they receive the A2 hot lots back, it'll be too late to fix many if not most if not all of the normal lots - if A2 is bad, they indeed just lost an unimaginable amount of money. Given how screwed up in so many ways they'll be if they need an A3 though, I'm not even sure that's their primary worry.

silent guy seems to be saying that wafers are parked before the majority of metal layers are constructed.

Actually, he's saying they are parked before ANY of the metal layers are constructed. My question is whether there is any reason to construct one, a few, or most of the metal layers while not actually finishing the whole process. Based on your assumed ordering, I think it wouldn't make much sense, but I'd appreciate a more expert opinion.

Really the question is about the meaning of "metal spin", what kind of faults you can fix

Well, you apparently can't fix borked ROPs Silicon layer changes being required for a product to work at all are relatively rare, although they do happen (MCP79/Ion, for example).

 

[Jawed]

As I said above, let's not be ridiculous. This is perfectly standard procedure. NVIDIA is *already* paying for GT21x per good chip and Morris Chang has explicitly said 40nm gross margins weren't as high as 65nm right now but they should improve to the same level as yields improve in the next few months.

I've not seen any statement that NVidia is paying per good GT21x, so quote, please?

Risk production is normal - but what's the quantity of chips for normal risk production? 10,000 wafers is 1,000,000 chips before yield and binning losses.

Selling per good chip doesn't require a "write-off" as Charlie claims, it's just standard gross margin accounting. And TSMC doesn't take the design risk if A2 doesn't work out because of design bugs, obviously.

That's assuming A1 is sufficiently bug-free to go to reviewers. That's a big assumption. The fact of the matter is that if they're willing to pay a bit extra every step of the way and take a bit extra risk, they can easily hard launch this thing in late November.

Like GTX295 was a hard launch?

Given how screwed up in so many ways they'll be if they need an A3 though, I'm not even sure that's their primary worry.

A3 was required for GT200b, and that's on a process that has been in full production since July 2007.

The way I see this, even if $50M are toast, NVidia should soak up the loss in its generally improving margins over the next two quarters.

Jawed

 

[XMAN26]

Like GTX295 was a hard launch?
Jawed

I could be mistaken, but I seem to recall GTX295s at Newegg, ZZZ and Microcenter on launch day. Hell, they even available all the while CHarlie "I'm a douche bag" was saying there were no more and would be a while before new stock was available.

But yet he remains amazingly quiet about the Rv740 shortage that happened recently. Had it been Nvidia, it would have been doom and gloom with they are desperate dumbasses everywhere.

 

[aaronspink]

I And before that he said "we hear Nvidia is paying a premium for each of the risk wafers" - so is it per wafer or per good die after all? Unless risk refers strictly to hot lots, which would contradict the rest of the article? And why would I believe they're being charged a premium when NV themselves claimed to have preferential pricing and Jen-Hsun and Morris Chang have been good personal friends for a very long time? This is patently absurd.

If TSMC is charging PGD and Nvidia is ordering a large quantity of early slot gate + planar only material. Then TSMC is likely charging them a LOT of extra for that gate + planar material. PGD pricing is based on projected yield curve improvements in a production environment which if you order a large quantity of the base layers before the fab techs haven even gotten a chance to do any defect correlation, you are effectively circumventing. So really it all depends on the actual number of set aside.

In a normal situation, you'll order 1 boat of wafers for hot lotting, and only process a couple of them to get parts for the initial bring up. You then have the better part of a boat available for later metal fixes. It sounds like Nvidia ordered more than a boat of set aside which would probably require additional costs.

As for Charlie's obsession with Global Foundries - here's a hint: it won't matter a single discrete GPU product coming out at either NVIDIA or AMD for a full *two* years. 32G is dead and both GF and TSMC are now claimed 28HP tape-outs will happen in 4Q10 - y'know, like 40nm tape-outs apparently happened in 4Q08?

Yeah, there is always a massive disconnect with what foundries claim and what reality actually happens. It used to just be in regards to process performance, now its getting into process functionality.