I'm aware of that. But the BER targeted by GDDR5 is probably worse than the target for DDR3 or FBD. That's my point. I'm aware that there is CRC over the interconnect, but the question is about the target BER relative to standard memory.
No, earlier you were quite explicit in questioning the
interconnect:
If you have ECC, I wonder if you need to worry about your MC<>DRAM interconnect a bit more and use something more robust than GDDRx?
GDDR5 was likely designed with a notion that bit errors are more acceptable than they are in the CPU/GPGPU world.
You keep on thinking up ways that this could work, but the reality is that it's a bad idea.
Hmm, well I'm not the one that paid real money for a patent application. Talk is cheap, eh? As long as I'm learning something I'm likely to keep prodding. Apart from anything else, I learn a bit more about the workings of existing stuff, and this discussion prompts me to ferret in this:
http://v3.espacenet.com/publication...T=D&date=20090205&CC=US&NR=2009032941A1&KC=A1
properly, some time...
We can't tell what NVidia thinks of the viability of these concepts, or what value/expectation NVidia once had. It might have been one of those recreational patents you see from time to time, "while we were building clouds we made some rainbows, let's patent them too."
You end up adding a lot of latency, adding power, adding cost, and you don't get a whole lot in return. That sort of thing is handy when you have a massive split in the industry (e.g. RDR vs. DDR), but it's pretty clear that the consensus is GDDRx for the high-end and DDRx for the low-end.
That split is actually very tortuous, though. It's one of the factors along with the implicit timeliness, that the patent application points at.
A factor of 2-3x performance between successive generations of memory, in a field such as GPUs where bandwidth demanded goes up by 2x every 2 years, but halo GPUs appear every 18 months or shorter makes for a treacherous mix. The "abortion" that was GDDR4 shows how treacherous it is to try to plan ahead.
There are a huge number of downsides and very few upsides.
Well, how do you price flexibility? Also, unless you're Intel, who can afford/cajole early-adoption of each DDR iteration, what can you do? AMD is forced to take a back seat with DDR iterations - apart from anything else, of course, the IMC has made the iterations more troublesome these past few years. Clearly the guys at ATI took the bull by the horns, yet it's still seen as good fortune how GDDR5 and RV770 combined.
I think that's a very insightful comment and I wonder what the data shows. I think you're right, and I'd be curious to see if that means that the low-end of discrete move upwards in the price stack.
Notebooks are selling more units than desktops, apart from anything else. And don't forget Intel, solely with IGP, commands the majority of the GPU market. Though it's worth noting that notebook and desktop systems can contain both IGP and discrete at the time of their original sale.
Since you are looking at the difference between two pins, any changes (e.g. temperature, bad pcb design) that equally impact both pins will cancel each other out. That makes EMI easier to handle for instance and can reduce the amount of shielding needed.
Differential signaling is also more power efficient (smaller swings in voltage on each pair can produce the same overall voltage shift).
One caveat here is DBI (and ABI) may be saving more power than is necessarily being credited. Inversion savings are effectively lost in a differential signalling system.
If you look at all the new interfaces introduced in the last 10 years, they have all trended towards diff. signaling: Rambus, CSI, HT, FBD, PCI-e, etc.
Well, as soon as someone isolates the pure interconnect power consumption of GDDR5, as opposed to the MC+interface+wiring+memory, then we might get somewhere.
Jawed
