Recent content by Toasty

I interpret it to refer to the different memory types supported by the MTRR register. From 2.13: "AMD Family 17h processor supports the memory type range register (MTRR) and the page attribute table (PAT) extensions, which allow software to define ranges of memory as either writeback (WB)...

See this article http://www.behardware.com/articles/847-7/the-impact-of-compilers-on-x86-x64-cpu-architectures.html What you are describing is the CPU dispatching feature in Intel's compiler. AFAIK, MSVC compiler lacks this.

Fixed point baricoords worked for me... plenty of precision there :)

OpenGL specifies exact pixel coverage rules. But rasterization results can still differ due to the following scenarios: 1) the vertex transformation pipeline may have slightly different results across GL implementations 2) clip vertices generated by clipping the primitive against the...

Instead of the interpolants you can walk the barycentric coordinates of the triangle then at each fragment directly compute the interpolants from them. Precision is improved since each barycentric coordinate will be in the range (0,1) for all covered pixels. It's more math ops but nothing that...

The OpenGL ES conformance test has a reference rasterizeration (pixel coverage) result that it compares to the framebuffer. For each triangle the geometry is generated randomly. It is possible to specify the number of random geometries to test. Therefore one could supposedly let it run all night...

My interpretation is something like the Folding@Home GPU client, which is an example of a massive shader application that demonstrates significantly lower power draw versus the majority of game applications.

Something tells me ATI paid $44.3 million for OpenVG and the engineering talent is just bonus. They have a very competent OGL|ES 1.x solution in Imageon and are certainly capable of leveraging their desktop GPU tech for OGL|ES 2.x. In my mind that leaves OpenVG as the only logical reason to...

If you do culling in NDC/screen space then you will also need to perform near-plane frustum clipping and perspective division prior to the cull test. For a HW pipeline this may introduce sufficient delay to mask any gains from the culler for all but more complicated vertex shading programs...

Try the code I pasted below. It requests a minimum of 1-bit stencil buffer. eglChooseConfig will return a config if it can meet (or exceed) these minimum requirements. If a config is returned you can query it to see how many stencil bits it contains, otherwise your platform likely does not...

That's walking distance from ATI corporate headquarters. You should solicit the folks at ATI who browse the board. :grin:

I've never actually seen a DS in action but I have a degree of experience with 3D on embedded devices. If you're doing a divide per pixel you shouldn't be able to see warping for any situation. It may be that the DS hardware does a divide for every 8 or 16 pixels (saving you from needing a...

In OpenGL architectures scissor testing is typically performed on a per-fragment basis. That's great if you have hardware that explicitly includes this functionality at no cost but sadly this is not the case for me. What I'd like to do is support glScissor at the transform+clipping level. I...

Does anyone know if the following conference proceeding: Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International is available anywhere online? There are a number of papers published at this years ISSCC involving the Cell architecture that I have been...

Correct. Back when R500 was R400 it was called Crayola, but it certainly isn't Fudo.