Recent content by Scott C

AGP Apeture has NOTHING to do with how much of your RAM the video card gets. The above quote suggests that the AGP apeture somehow controls how much physical memory the video card gets. I had a TNT1 with system RAM of 64MB and apeture set to 256M. No problem, 32 bit hardare has access...

Well, a PowerVR type GPU would do MSAA for free. Perhaps 4x or even 8x at the same speed as no MSAA and ATI and NVidia can't keep up with that, bandwidth saving techniques or not. The bandwidth saving techniques (early z, heirarchical z, and frame buffer compression) still don't outweigh...

Where did I say they _should_ do it that way. And you provide no reason that they should go any smaller than this (latency is not a reason, I'll explain below). IF is the key point. If they targetted a FP add as the gating factor it would be slower. They absolutely don't make a pipeline's...

No, because a CPU is limited by its integer add speed not its multiply speed. So I was saying a dot product takes 5x longer (4 cycles longer) than an add, or 20% clockability if in one stage. Yeah, my mistake. 8 inputs, 4 mults, 3 adds. And about cross products, the point was...

Uh, multiplies are ~ 4x longer than adds in time to execute (logic cascades). An adder can be really fast because most of its work can be done in parallel. A multiply is significantly more complicated. Just look at the latency of instructions for FP code in most CPUs. Adds are...

Exactly. Dot products are a component of a vertex transform. And in addition they are useful on their own (lighting). Interesting how a Dot Product and a bilinear filter blend are roughly the same ammount of work for two different pipeline stages. Could it be that on today's processes a...

Perhaps, but you are still arguing in what I see as completely orthogonal to my main points. I'll try to be clear and less wordy this time. Most certainly I agree that the latency has driven pipeline length. The root question is clockability however, which has not driven pipeline length...

You are clearly either not understanding, or not paying attention to the difference between a Pipeline Stage and a Pipeline and thus entirely misinterpreting my post. Note the very critical distinction: A Pipeline STAGE does a bilinear filter per clock (input is four texels, output...

I'm saying a single transistor can switch in a length of time equivalent to hundreds of Ghz. That is, 500Ghz = 1 / 2ps. A transistor can take 2 to 3 ps to switch (333 to 500Ghz rate). However, a single pipeline stage takes a lot longer than the switching time of a single transistor, it is...

The above indicates a significant misunderstanding of how a chips Mhz rating relates to transistor switching speed. Transistors in nodes below 90nm can switch at almost 1 Thz (1000Ghz), and this is the same for CPUs and GPUs, though Intel and AMD's are faster and more highly tuned...

Um, yeah how would this kill competition? The details of the architectures and how they achieve a more unified, consistent set of features will differ markedly. Is a Pentium 4 the same as an Athlon 64 just because they both run x86 with MMX and SSE2? I don't see how a more consistent...

Quick, name the top 3 PC graphics core vendors. Quick, which ones have a DX9 (longhorn) part? That's my guess; might as well choose the most optimistic one I can come up with. ---------- Oooh, Rendition 4400. I so wanted one of those back last mellinium some time. Silly Micron...

Re: Trilinear single mip level Optimization not always chea You must take more than 4 samples in order to have both spacial filteringo n one detail level and smooth detail level transitions to prevent mip level discontinuities. Lets think about a polygon with a texture, that is paralell...

That is assuming that the AI is the reason that it slows down when characters are on screen (botmatch vs flyby demo). I don't know about this release, but on the previous UT release I got acceptable framerates on a 1200Mhz system by turning down the shadowing options, and turning off EAX...

I didn't have time to wade through several hundred posts, (I despise this forum format for any sort of catch-up on discussions) but my point is simple. If ATI is "disabling" the bilinear anisotropic or trilinear modes when color mip maps are used, this may not be cheating. It is PERFECTLY...