Recent content by pMax

...I apologize, but I had to do it ;-)

...yet i miss why people are discussing about bumpers and so on: those terminations must end in DCT/PHYs, do you multiply them as well (edit: rethinking, they were thinking of interconnecting the varous MCs with bumpers, maybe?)? Plus, as they are talking of coherence, that thing happens in the...

I tried to follow up this discussion, but I do honestly not understand why are you talking of the bus interconnects. AMD stated they moved to a coherent bus: coherence is made at MC level access, as at DC level is already too late. So, given they were doing coherency between the GPU MMU and the...

...uuuh? is he still active on the field? God he must be old by now...

yeah, that is a curious question. In my limited experience, biga** game engines have an heavy frontend with some #ifdefs and a generic backend layer where they implement the effective renderer (i.e. DX, OGL, PS). While I understand the costs of adding one is not small, I miss the reason of why...

costs skyrocketed. Now to get out with a decent game you need like 80-100 guys for a few years. Factor in all the accessory costs, and you see the results. And the game I am thinking about is not AAA, just a good (and very nice) game.

...mah. PS4+ VITA was something similar but: 1) the handheld cost with a decent tegra on it. 2) the docking cost with a powerful processor in it. 3) they promised to have games like PK:GO on their NX - it means you need internet+GPS anywhere on handheld, so SIM card. ...it is not going to be a...

Thanks, I wanted to understand where DX11 was differing i.e. from console approach. It is for DX12, but i see it quite compelling to my question/case. ...wait: slide 39 reports lot of KMD usage - which was my raised point before (I think with another guy, OpenGLguy?). IF all the work is moved...

:D ...how bad you are against skiddies.... Spes Ultima Dea, remember :p OT: the block in chip's image is attached to the memory bus, it seems. So it can be: ARM processor for security (supposing it is using ARM for security, of course) Any extra processor/stuff not yet embedded in GPU design...

hmm... i remember longhorn model, at least vaguely, yeah. Thanks for the clarification. I was honestly supposing that in windows a blocking issue was having DX to walk the kernel borders all the time,as there is a huge work in kernel for DX, and so OGL

...just curious, as I've never gone deep with Vulkan/DX12: do they work mostly using a user-mode driver - i.e. writing commands in a user mode command queue(s)/rings/whatever? Or do they still involve many driver calls (except for non-trivial, special tasks like vmemory allocation/mapping that...

Why? A page fault will force you to load from disk anyway, so where's the heck? Do you talk about dGPU systems with some textures held in CPU RAM? I do not see exactly the point with HSA -except, of course, if the HDD doesnt have the 64k read sequentially at hand. The CPU trap triggered by the...

Oh come on, you get that only in loops where the intel chip can abuse the mop cache they did put after the decoder. And you are comparing a core with a hard limit set by the decoder and just 2 integer units to ones with all the execution units alive and kicking...

...only conceptually? hihi... AFAIK it works, especially with GoDaddy ;)

As far as I understood, the only drawback was the fact you could not easily do audio and physics in the GPU due to latency issues. The new GCN microcode update, retroactive to GCN 1.1+ if I remember, address exactly this. Given that devs can easily monitor GPU occupancy, it would be something...