Recent content by OlegSH

Depends on what you're comparing. In still scenes, they all look better than native resolution with TAA even with the 4x upscaling factor. Simply because TAA uses color clamping, a lossy algorithm by definition, which cannot resolve pixel sized features and removes a great deal of information...

Increasing the framerate by a factor of 2 to 5 times without noticeable quality losses, or even improvements in some cases, is the most transformative gaming application one can imagine in all senses.

Typically, such minor changes result in an average performance improvement of around 0% when tested across various benchmarks. Updated counters are likely here to address corner cases in a few titles, where they might improve the average framerate by a percent or two. The better caches are...

There's been papers on this from intel as well. Since BVH is fully built in sw, there is nothing stopping it from appearing on NVIDIA too, of course.

I don't see any discrete RDNA3.5 GPUs on market, so it does not. NP. What's the deal with frequencies in the PS5 Pro? Are they not aware of the magic PPA of RDNA3.5, or are you missing something?)

The big kaboom does not matter at all as I was talking about current products. The thing'd better be well-architected. Simply relaxing the timings will hike the power, possibly with minimal performance returns, despite the high frequencies.

With that fmax juice, the only thing that would have been destroyed would be the power efficiency) Exactly the reason why neither AMD nor NVIDIA went for this. As for the fmax, to what does the 4090 overclock under nitrogen, over 4 GHz? It seems Ada has left more juice spilled on the table...

Funny) The least of RT's limitations is the LLC. Consider an Ampere vs. RDNA2 as an example of what I'm talking about. The least effective method for speeding up random pointer chasing in a huge data structure (which doesn't typically fully fit into the cache at all) would be to increase the...

An old trick used by every startup since forever. To me, these are truly meme benchmarks, or more like a move of desperation)

Quoting AMD data sheets here. So, do you imagine them having a dedicated 900 GB/s connection from each GPU to any other?) Of course it will still require hopping through all the other GPUs to achieve the 900 GB/s bandwidth and waiting for the slowest one. Lol, so simple that they can't even...

That's just a bunch of theoretical numbers slapped together. The effectiveness of the ring p2p connections for the 8 GPUs setup is certainly in question without any benchmarks. Given the scarce topology information they provided, achieving the claimed 900 GB/s p2p bandwidth may require going...

Even this can be limited by the bandwidth between the accelerators, as AMD doesn't seem to provide full speed bandwidth between all accelerators due to the absence of an NVSwitch analog.

Does AMD even have a switch for large-scale training? Some raw specs may look good on paper, but their relevance for large-scale training without infrastructure is beyond me.

Ping-ponging the frame back and forth between the GPU and NPU within the CPU would have been disastrous, so it should use the discrete GPU for these purposes whenever it's available :)

If this was addressed to me, of course, I was referring to spatial upscaling in the context of temporal upscalers. Spatial upscalers are utilized in the core loop of TAAU and all other temporal upscalers. When TAAU/FSR/whatever else fails to accumulate samples for various reasons, you will see...