Recent content by Jeff B

Yeah, it's a hack. Most algorithms I'm aware of use a diagonal in a 2x2 quad, but it was simpler and faster to just look at dU.

No, I think a ring bus with a write-back/write-invalidate protocol would still be better. I got it basically working, but started running into edge cases, some of which I documented here: http://latchup.blogspot.com/2014/07/messy-details.html For the simpler write-through/write-update...

Yes, it does need to spill during function calls. I don't think the overhead of that dominates compared to framebuffer, texture, and data structure access, but I haven't measured that explicitly. That might be an interesting experiment. I've posted some rendering profile information here...

Yeah. Combinational logic finds the next ready thread each cycle. RTL is here, if you're curious: https://github.com/jbush001/GPGPU/blob/master/rtl/core/arbiter.v That's a good question. I've played with that a bit, but didn't see much difference between switch every cycle vs. run...

Yeah, basically, although this demo is more of a texture engine than a rasterizer. I built them from scratch. The floating point pipeline is four stages. I broke it up this way to spread out the logic delay and get a higher clock speed, at the expense of more overall latency (ie the result...

Yeah, an FPGA tends to suffer from a lot of delay in the routing fabric that connects the logic elements together. For example, the UltraSparc T1 chip runs at 1.4 Ghz, but the same design synthesized on a Xilinx FPGA has a maximum clock speed of around 75 Mhz. I've seen preproduction mobile...

Thanks. I'm using the Terasic's DE2-115 board. The OpenCL stuff is interesting; I hadn't looked at that either. It looks like it compiles the OpenCL kernel into a FPGA bitstream. It's doesn't have quite the flexibility of a GPU, but would be useful for dedicated applications.

I posted about this project last year, but I've made some progress since. First, a quick demo: This is an experimental GPGPU I've been working on running on FPGA. It utilizes a Larrabee-esque programming model that is software focused. Full source (RTL and tools) are available here...

I'd certainly be interested to see what you come up with if you do. Let me know if you have any questions.

Thanks :) This has been a solo hobby project so far. My background is in software, so it has been fun learning more about hardware. There have been some interesting discussions here and elsewhere about the benefits/drawbacks of more programmable architectures like Larrabee vs. ones that rely...

I've been working on a project and I thought people might find it interesting. It is a GPGPU hardware architecture, inspired philosophically by Larrabee (although the ISA is quite a bit different). I have implemented an assembler, C emulator, and synthesizable behavioral verilog model...