Recent content by huebie

Agreed and since the geometry stages in the pipeline aren't decoupled from the topology there is no feasible solution or explaination for 21 GE. With 28 you are fine when dividing it by 7 which is 4 (math skill +10.000 :D).

I wouldn't bet that the 21 is the physical number of geometry engines since the Titan V is a cut down chip and this should be a fixed wired unit (and not a network approach). Did you considered this option? The visible trinangle per clock is slightly above of 2 because the frequency is not...

Just to be clear: i meant one type of layout for a PCB, not a single PCB, with a GPU and GDDR5X+GDDR6. :D I read my sentence twice and felt it should be mentioned... Happy new year. :-)

I'm pretty sure there won't be a mix of GDDR5X and GDDR6 on one PCB. The pinout and the pincount are different, so you will need at least a modified PCB. The controller side is a different question. I think it should be possible, but not sure <yet>. Have to check specs back again, but i'm really...

Ah, thanks. My brain kept the wrong date since the last months past by so quickly for me. :D G6 needs a (very) different MC since the i/o config is x8/x16 instead of x16/x32. A conventional MC has 2x 32 bit lanes for each channel and module (correct me if i'm wrong - and let's keep outlaws such...

Thanks for the explanation. So it is a common usecase in various game-titles where devs can gain performance improvements too. Tier 1 sounds morelike a software feature rather a hardware feature.

So a loop of two view ports (where does it loop?) for VR would take twice the time of one (2D screen), but less time compared to "old methods" (e.g. sending the same draw call again). For my understanding it primarily lowers CPU-Usage; am i right?

Already read this article but don't know the practical usecase. :D That's what i was up to.

Afair Micron was able to run G5X with 16 Gbps in 2016, too. But it was not reliable enough, i think.

I think the main reason is, that NVIDIA and Micron teamed up behind closed doors and came to public when the results where promising enough and a concrete product was already in mass production. Other manufactures such as Toshiba or Hynix wouldn't have sold a single G5X module since the few...

There is no "Micron-proprietary stuff". See JEDEC spec sheet. GDDR5X was validated with 14 Gbps and GDDR6 is the next iteration as it is mostly G5X. Iirc the tx/rx boundaries are more strict to achieve higher clockrates. This is obtained by a broader clock noise reduction or for my understanding...

Can anybody explain what D3D12_VIEW_INSTANCING_TIER_1 is and why it is 1 in dev mode and 0 in normal mode? :D @donjulio: Welcome to the underground of the 'nerd graphics elite'. :-)

Is there any technical paper to proof that? But yeah maybe you are right. Anyway: the story with the secondary GPU was denied by big N. So we wont see much better graphics...

PCIE 3.0 with at least 4 lanes? :?::no:

I think it depends on whether they are using a secondary GPU in the station or not. You would need at least PCIE or something equivalent that is capable of unplugging during a running session. The Tegra itself has not very powerful I/O for external comms. I hope it is not only one Tegra, since...