Recent content by DmitryKo

OK then, I will stick to DXGI for now, and use DXCore to query hardware attributes and select the minimum feature level, and also add a command-line option to set it. This will be added in the next release of my tool once a new Agility SDK version rolls out, hopefully this June after Bulid 2024...

AFAIK, NPUs are not really supposed to be directly programmable by the application developer, but rather by each vendor's video driver programmers who would adapt it to the specific needs of middleware libraries and runtimes. For example, DirectML and WinML are designed to use Direct3D...

I've added the necessary C++ plumbing to query DXCore adapters with IDXCoreAdapter::GetProperty(), and adapter LUIDs do match between DXGI and DXCore "core compute" adapters on the same graphics card (and the WARP12 software renderer) - so there's a good chance NPU devices will be visible as...

FYI I've been experimenting with DXCore, and it's actually available for regular Win32 'desktop apps', like most WinRT APIs today - so there is no need to switch to the UWP app model, and you can suppress DXCore.dll exports with LoadLibrary() or delay-load linking. It's still a typical WinRT...

NPU devices should be able to run compute shaders according to Microsoft Learn documentation on feature level 1_0_CORE, but you have to request this specific level and not any higher feature levels when creating the Direct3D12 device, and also enumerate MCDM adapters using IDXCoreAdapterFactory...

After open-sourcing HIPRT 2.3, AMD intends to open-source more parts of the ROCm 6.x stack and publish internal documentation on hardware features: https://www.phoronix.com/news/AMD-More-OSS-Hardware-Docs...

While it was tempting to post the news on April 1st... it's no joke, we're now at #250 with 9.53 billion points, almost 2 months earlier than my estimate - so at our current rate of ~65M points per day, it's exactly 2 months before we enter the Top 200! :runaway: Rank Project Team Name...

There is nothing in that patent that even mentions DXR or any kind of external block storage. What they propose are methods to pre-build BVH nodes from low-detail geometry then store the actual high LOD geometry in child nodes placed in system memory, and let the CPU upload high LOD nodes into...

Mesh shaders in AMD RDNA™ 3 architecture Lou Kramer (Member of Technical Staff, AMD) Max Oberberger (Senior Software Engineer, AMD) [Slides – 2.7MB PDF] [Animated slides – 115MB PPTX] AMD GD C2024 sessions: https://gpuopen.com/events/amd-at-gdc-2024/

https://gpuopen.com/learn/mesh_shaders/mesh_shaders-index/ https://gpuopen.com/learn/mesh_shaders/mesh_shaders-from_vertex_shader_to_mesh_shader/ https://gpuopen.com/learn/mesh_shaders/mesh_shaders-optimization_and_best_practices/...

GPUOpen has a dedicated page "AMD at GDC 2024", with links to individual videos and session slides in .PDF and .PPTX formats: https://gpuopen.com/events/amd-at-gdc-2024/

Great - you should be making ~18M PPD with your energy-efficient hi-tec folding heating rig! 🔥 And your room is probably 30 ° cooler too... ❄️ you should really consider another RTX 4090 as a backup heater! 🔥

Graphics nodes were published right in the intitial Work Graphs specs v.43 - though last December they added Work Graphs Tier 1_1 to indicate support for Mesh nodes, initial implementation is still not public. Draw nodes / DrawIndexed nodes are also specified, but not yet implemented.

Same for me, even though relevant AMD Adrenalin setting remains enabled. I suppose this option should return after restart though.

I've updated my tool to support new features in Agility SDK 613 (and Windows Insider Germanium builds 260xx) - this is how the AMD Adrenalin preview driver reports them on my Radeon RX 7800 XT: RecreateAtTier : D3D12_RECREATE_AT_TIER_NOT_SUPPORTED (0) WorkGraphsTier : D3D12_WORK_GRAPHS_TIER_1_0...