Toshiba's 65 nm fab capabilities...

[DeadmeatGA]

http://www.siliconstrategies.com/story/OEG20021202S0091

Toshiba's eDRAM and SRAM size at 65 nm

eDRAM : 0.11 um2
SRAM : 0.6 um2

These are certainly small numbers, but not radically better than competitors. NEC's UX7D will have an eDRAM cell size of 0.15 um2 for example. Yea, that's a 26% improvement over its competitors, but not drastic enough for Toshiba to do things that others can't.

Another notable piece of information is that this eDRAM cell is supposed to enable 256 Mbit density on a chip. Does this mean GS3 will have 32 MB or does 32 MB take up the whole chip, thus the actual eDRAM size in 24 MB range????

 

[Grall]

Yes, with "only" 26% smaller DRAM cells, Toshiba certainly cannot do things other manufacturers can't, such as fit a quarter more DRAM onto a chip compared to competitors...

As for your 256mbit comment, it is assumed they meant 256mbit along WITH whatever else they'd want to add on the same IC. 32MB dram is achievable TODAY on a die far smaller than the 280sqmm you proposed for a Cell processor, so obviously the RAM would not take up the entire real estate of the chip.



*G*

 

[SMarth]

It's much more then 26% better, don't forget that's a square surface. But even so, 26% would be quite a bit more then the competition in just about anything

 

[incurable]

It's much more then 26% better, don't forget that's a square surface.

Ahem, what you say?

But even so, 26% would be quite a bit more then the competition in just about anything

Yep.

cu

incurable

 

[Panajev2001a]

http://www.siliconstrategies.com/story/OEG20021202S0091

Toshiba's eDRAM and SRAM size at 65 nm

eDRAM : 0.11 um2
SRAM : 0.6 um2

These are certainly small numbers, but not radically better than competitors. NEC's UX7D will have an eDRAM cell size of 0.15 um2 for example. Yea, that's a 26% improvement over its competitors, but not drastic enough for Toshiba to do things that others can't.

Another notable piece of information is that this eDRAM cell is supposed to enable 256 Mbit density on a chip. Does this mean GS3 will have 32 MB or does 32 MB take up the whole chip, thus the actual eDRAM size in 24 MB range????

Deadmeat, so you have re-started your campaign to try to put down SCE and their future products ?

About the PSP software abstraction and the CELL comment you made in the last thread, if you go look to the other interview Ken Kutaragi made about CELL, posted in this very forum quite recently, he said that the software approach would be the one they have chosen for PSP: the Founder PS libraries.

 

[Deepak]

DM why do you post only about SONY/PS2/PSP, even Chap doesn't post only about XB....

 

[Panajev2001a]

DM why do you post only about SONY/PS2/PSP, even Chap doesn't post only about XB....

What can I tell you ? He is a SCE fanboy

 

[SMarth]

It's much more then 26% better, don't forget that's a square surface.

Ahem, what you say?

Whle the reduction is 26%, a 0.11um2 dram cell will occupy only 53% of the space of a 0.15um2 cell. In other words, for the same die size, you "could" pack 86% more dram cells.

 

[Thowllly]

It's much more then 26% better, don't forget that's a square surface.

Ahem, what you say?

Whle the reduction is 26%, a 0.11um2 dram cell will occupy only 53% of the space of a 0.15um2 cell. In other words, for the same die size, you "could" pack 86% more dram cells.

No. If these number were the width and heigth of the cell (0.11um x 0.11um vs. 0.15um x 0.15um) then you could pack in 86% more cells.

But the number given is allready for the area of the cell (0.11um2 = ~0.33um x 0.33um and 0.15um2 = ~0.39um x 0.39um, if the cells are square)

So you can only pack in 36% more cells (in a 165um2 area you could have 1500 0.11um2 cells or 1100 0.15um2 cells. 1500/1100 = ~1.36)

 

[SMarth]

But the number given is allready for the area of the cell (0.11um2 = ~0.33um x 0.33um and 0.15um2 = ~0.39um x 0.39um, if the cells are square)

Doh!, though it was the size, not the area...
36% is still pretty good tho.

 

[DeadmeatGA]

...

36% is still pretty good tho.

No, it is a 26.7% reduction. When you take the NEC cell size as the base, Toshiba has achieved a 26.7% reduction relative to NEC.

 

[SMarth]

Re: ...

36% is still pretty good tho.

No, it is a 26.7% reduction. When you take the NEC cell size as the base, Toshiba has achieved a 26.7% reduction relative to NEC.

It's not about reduction, but about how much more cells could be pack on the same area in reply to Grall.

 

[nonamer]

Looks like Toshiba's eDRAM is pretty good, meaning it's very dense. Any data on IBM's and Intels eDRAM/eSRAM? I've heard that they have pretty dense stuff too.