Taking it to the limit: 35nm?

F

Frank

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Where is the absolute lower border for generic lithography and cmos FET transistors? 45, 40 35 or 30 nm?

With quantum computers still being a distant possibility, that leaves increasing die size. Even multi-chip solutions. But in any case, Moore's law ends.

What will be the next target? I go for big, slow and short-lived, but very cheap, broadly useable and mallable biological compounds. Although mechanical computers are possible as well.


The main distiction will probably be: are nano-mechanics biological based (ie: tweak the DNA of cells), or are they semiconductor based? Both are poor candidates for actual nano-machines.
 
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I think 22nm is very optimistic. It's very unlikely that it can be done.
 
I think 32nm would be the lowest limit for the mass production of ~ several billion-transistor processors (not counting multiple chips on a package). Heat dissipation might become too much of problem to make such large-scale chips anyway.

The main issue as I see it is once you start getting to sub-20nm, material properties change quite drastically. You might be able to somehow produce structures consistently at that size, but then material properties are going to bite you in the butt. For instance, crystal lattice structures will change. Even currently there are some issues with silicon crystal lattices with which to deal in order to achieve anisotropic etching, and these are just different planar directions. At sub-20nm, you'll likely be seeing a change in the entire crystal lattice (e.g. cubic to hexagonal etc).

Not to mention the optical material and devices needed for focusing the lasers... Immersion Lithography (IL) seems promising in extending the life of Deep UV lasers as promoted by IBM and now AMD for 32nm. They "only just" need to find suitable fluids with a higher index of refraction while also making sure they're compatible with the lithography process (resist layers, exposure etc). It'll be interesting to see if they will adapt IL for Extreme UV, which itself requires a rather complex system of mirrors; at EUV, the considerations are mainly in focusing the beam with appreciable loss in power by the time it gets to the target hence the use of mirror resonator systems.

Perhaps X-Ray Lithography might be an alternative solution, though the problem there is beam penetration and again, material considerations...


...but again, useable transistors when the material properties themselves change? I hope they have a good chemical and materials engineering group...

... just pseudo-random thoughts. :oops:
 
It will go below 32nm I assure you the money will be there for and it will be done if the price is right. The change in material properties goes both ways as it can be good and bad. Also there are technologies such as quantum entanglement lithography which 1/2 the effect wavelength.
 
I remember seeing a TEDtalk or a speaker who was a TED speaker give a talk on what will happen after 32nm, and his opinion is, 3D. Of course, Eric Drexler thinks nanorod logic, and some people I know at IBM think that when quantum effects become predominant, they will make design harder, but actually boost performance if you can leverage them, the issue is the complexity of the design software.

I'd like protein folding. It's hellishly complex, and ultra-CPU intensive to model, but if you had the tools to model and design proteins in reasonable time, it would be enormously, staggeringly beneficial.
 
I think there are enough interesting solutions out there to scale further downwards. Rather than scaling itself, I'm more worried about Moore's Law specifically. How likely is that we can find the necessary solutions to the problems plaguing scaling *and* keep pace with Moore's Law?

Intel believes they can get 32nm in mass production sometime in 2009. So that's still in line with Moore's Law. But I've seen reports of 2012+ for 22nm, so there we're already at 2.5-3 years. Eventually, I wouldn't be surprised if the industry standardized on the Square Root of Moore's Law instead. One half-node every 2 years, for example... But we'll see, this is just pure speculation! :)

Besides that, I would tend to agree that 3d/chip stacking along with process cost and power reductions is a very interesting possibility. I think the two would have to go together though, because there is no reason to believe costs and power at a given node can scale infinitely.
 
I'd like to remind everyone in this thread that Moore's original statement was that chip complexity will approximately double every two years. Note that he did not specify how that complexity would come about, but he did make it pretty clear that he considered transistor count as a valid measurement of complexity. As such, when the term "Moore's Law" was coined by a Caltech professor, it was essentially linked to a doubling of transistor count every 24 months.

For essentially ALL of the past and the near-term future, that increase in transistor count has been made possible by lithographic process improvements. However, you don't necessarily require a process shrink to double chip complexity.

Every time Moore's Law comes up, I feel the need to remind people that it isn't hard-linked to lithography, and as such, lithographic improvement is not the sole driver of Moore's Law.

That is all :)

P.S. Here's some reading if you want more details
 
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bloodbob said:
It will go below 32nm I assure you the money will be there for and it will be done if the price is right. The change in material properties goes both ways as it can be good and bad.
Click to expand...

It really does come down to cost doesn't it? ;) I'm sure there are banal things about the different material properties; the chemical and material engineers will just have a fun time with working out how to optimize for electrical considerations. :p

Still, at that feature size, it's not going to be as "easy" to make sure that all the molecules are behaving as they should be between the different types of lattices versus planar directions. Getting everything consistent and then making it work is going to take some real awesome voodoo ( from my limited POV though). I'm always worried about cost, but yeah they'll try it out eventually. :oops:


Also there are technologies such as quantum entanglement lithography which 1/2 the effect wavelength.
Click to expand...
Care to shed some more...light on that, please? :) I didn't quite understand what you were trying to say :oops:
 
20 years ago, people were forecasting issues because fab capital costs were spiraling. People were up in arms over the fact that fabs were going to cost a billion dollars! I saw predictions that eventually Fabs would even cost tens of billions approaching the cost of expensive military and aerospace projects.

However, even a capital investment of $10 billion offers a positive ROI given the increasing size of the world market (another 3-4 billion people need CPUs :) ), and the fact that although bleeding edge chips move to new process nodes quickly, the tail end of mainstream and low-end chips moves up to take its place, so the investment isn't lost after 2-3 years.

It is possible that at some point, the ROI will be negative, but it won't destroy the industry. The ROI for aerospace and space is already negative IMHO if you subtract out government subsidies, and I think that's the route you'll see, which is government/consortia stepping in to fund R&D over long time periods whose lifespan is too short for fast ROI.

At the very least, the NSA will be there to fund black-fabs. :) (check out RSFQ and COOL0 and the numerous NSA backed quantum computer projects)
 
I agree that the price / performance ratio will keep on getting better.

But, a chip with structures less than 30 nm will behave quite different than the current ones. Atom placement and quantum tunneling will start to interfere below 45 nm.

When you enter quantum tunneling territory, you start working with single electrons, or very small batches. Which need to be encapsulated inside a magnetic field to travel dependently to their destination. And you need good retainment for your gate charge, which will bleed all over the place in such a scenario. Which requires a 3D approach, in which you look at the magnetic fields next to the resistance.

Lithography shows interference patterns when you go below half the wavelength, which are a sizable part of the lowest size structures at that resolution. So, borders aren't straight, but "wavy". And because we're working close to atomic scale, surface tension (depending on the orientation of the molecular grid) makes it hard to create smooth surfaces.

Atoms do wander around a tiny bit, and at that size it will become noticeable. And you don't want your nice chip to stop working because some atoms that were placed periously at production relocate a bit, and change the magnetic pathway of a trace, or bleed electrons in or from a gate capacitor.

If you need to double the size of your structures to be able to supply the magnetic encapsulation and prevent small defects (over time), it might make the overall structure less dense than one made at a lower resolution.


Still, there are many ways to fix all the problems, and many possible directions to go other than lithography. And either way we're developing machinery that can manipulate structures at such a small size, that it borders at the biological.

I am very curious what will come out of it! :D
 
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