Rv670 and rv770 : texture cache?

C

codedivine

Regular
So I found 2 public presentations given by AMD employees which give a little bit of hint (but are very confusing) about the size of cache:

a) http://www.sharcnet.ca/events/ssgc2008/presentations/yang-sharcnet-final.pdf
On slide 11 : It shows that all 4 texture units on rv670 share a single L1 cache and quotes unified 32k L1 texel cache and 32k structure cache unfiltered. It also quotes shared 256kb L2 cache.

From the above, I would understand that the TOTAL L1 texture cache is 32kb and not 32kb/TU as quoted in many articles on the web. Is this correct?

b) In a presentation by Mike Houston he says for Rv770 : "2.5x increase in aggregate L1 compared to ATI Radeon™3800 series"


I take this to mean that the total L1 cache on rv770 is 2.5*32=80kb giving 8kb L1 per SIMD.

Comments? Info? Anyone has any testing results?
 
In the launch presentation for HD 4800 series on RV770 architecture on page 9 is stated:
"L1s store unique data per SIMD
2x increase in effective storage per L1,
5x increase overall"

From the "effective" I'd assume that to include some kind of compression. OTOH, if someone would be really paranoid (and given that this presentation comes from marketing), one could argue, that this refers to bytes per Texel.
 
The 2.5x increase comes from the increase in the number of SIMD's from 4 to 10 (320 streaming processors to 800 ...)

On RV670 the L1 cache was 32kb shared among 4 SIMD's

On RV770 each SIMD has its own dedicated 8kb L1

2x effective may be due to better compression, then in total the 770 makes 2x better use of the 8kb per L1, and has 2.5x as much L1 in total, or 5x "effective"
 
[I was going to write what Everett did...]

On "2x effective": This could also mean (again: my quote comes from marketing!) that they're reffering to available bytes per texel per time. Given that RV770 TUs aren't single-cycle FP64 any more, effective storage for FP64 texels would have double again. ;(
 
Yeah 8kb/SIMD looks right.
Now that still leaves the question of L2 cache size on rv770.
Anyone have any pointers on that?
 
codedivine said:
Yeah 8kb/SIMD looks right.
Now that still leaves the question of L2 cache size on rv770.
Anyone have any pointers on that?
Click to expand...
Nothing substantial, but given that marketing uses to brag about bigger number on any occasion (in every company, mind you!) and they failed to mention bigger L2 as well, I'd assume L2 size to still be 256 (divided into 4x 64 kiB blocks). The checkerboard pattern with 8x8 blocks per L2-partition in the marketing slides might be an ever so slight indicator to this size also:
 
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