Maximum die size?
- Thread starter Lonbjerg
- Start date
There is, and it's mostly governed (as far as I understand it) by the optics that drive the chip lithography, which define the range of focus for the beams. I've never quite understood why it's the 'reticle' limit, although the reticle on the optics must affect focus in its own way. The resident chip nerds should be able to tell you more.
Maximum die size is therefore foundry and process dependent. At a guess, after FPGAs it'll be GPUs that push the limits more than any other fabbed chip type. GT200 was often mooted as being at or near TSMC's reticle limit for 65nm.
Maximum die size is therefore foundry and process dependent. At a guess, after FPGAs it'll be GPUs that push the limits more than any other fabbed chip type. GT200 was often mooted as being at or near TSMC's reticle limit for 65nm.
As far as I know, the reticle limit for TSMC on their recent processes is around 600mm², I think Intel's is around 700mm², judging by Tukwila's size.
Edit: this post is apparently highly rated by Google, which is unfortunate because I think I was wrong. TSMC seems to be able to manufacture bigger chips than that.
Edit: this post is apparently highly rated by Google, which is unfortunate because I think I was wrong. TSMC seems to be able to manufacture bigger chips than that.
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The biggest chips are indeed CMOS sensors and I don't know how they are built.
Intel has produced a 700mm2 chip in 65nm, which is pretty damn impressive.
The real issue is that you can only expose so much area of the wafer in a single exposure. To use two (adjacent) exposures, you'd need to have everything line up perfectly. Remember all your metal lines running from exposure1 need to connect to exposure2, and if those connections suck, it could impact frequency.
Now interestingly enough, the industry is moving to double (and soon triple) exposure at advanced geometries. However, they are worried enough about overlaying two images on the same area, that nobody is really screwing around with adjacent exposures.
DK
Intel has produced a 700mm2 chip in 65nm, which is pretty damn impressive.
The real issue is that you can only expose so much area of the wafer in a single exposure. To use two (adjacent) exposures, you'd need to have everything line up perfectly. Remember all your metal lines running from exposure1 need to connect to exposure2, and if those connections suck, it could impact frequency.
Now interestingly enough, the industry is moving to double (and soon triple) exposure at advanced geometries. However, they are worried enough about overlaying two images on the same area, that nobody is really screwing around with adjacent exposures.
DK
Amdhal tried that iirc. Didn't work out that great for him.
A Full Frame sensor is 864mm² (36 x 24 mm) and the Medium Format sensor is 1977mm² (50,7 x 39 mm).
aaronspink
Veteran
Ultra large CMOS sensors are built with multiple stepping exposures with fairly conservative inter-exposure design rules. All very modular, etc.
That makes sense, I bet they charge a metric shit ton for each one.
Do you know what kind of design rules they have?
I imagine they only allow a few really big metal interconnects between exposures, maybe something like ~250nm.
DK
aaronspink
Veteran
Varies widely, like 10000x for a given part. They are also generally fabricated in older processes since they have real physical size limitations and most of the new processes have too much variability. They have pretty high yield recovery due to the variety of markets that they will sell a given design into from the consumer to the ultra high end scientific. They'll do things like measure the uniformity and sensitivity of a given part and determine what part of the market it will sell into with the most uniform and high sensitivity parts going into the scientific/astronomy markets and selling for upwards of 10s to 100s of thousands and the heavy yield recover parts selling in the low hundreds.
Processes are generally > 100 nM which makes sense since their cell sizes are generally in the 4000nM x 4000 nM and up range.
I think most modern chips are produced using Steppers.
http://en.wikipedia.org/wiki/Stepper
A Stepper uses a mask plate that has the information you want to transfer to the wafer that is usually 10 times the size of the actual transistor/line sizes, and is then photo-reduced by a 10x lens system to expose the wafer.
Hence, if you have a chip size of 20 x 20mm (~ 0.8 x 0.8 inches) then your Photomask plate has to be 10 times the size, or 8 inches x 8 inches square. The whole stepper machine is probably designed around a maximum reticle/Photomask plate size. Hence, that particular stepper machine is probably hard limited to a particular maximum chip size.
The stepper machine then "steps" around the wafer exposing each chip one at a time, hence the name.
You can use other stepper machines that are designed for larger Photomasks perhaps, but these are very expensive pieces of equipment, so it's not something that's easily done.
As far as making the whole wafer a single chip, if you are using a 10x stepper there is no way to do this. You would have to go back to the old style of using 1x Photomasks, and I don't think anyone is doing that at 40nm and below.
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spacemonkey
Newcomer
A few years ago DALSA build this monolithic 111 megapixel CCD sensor
100mm x 100mm (on a 150mm wafer).
100mm x 100mm (on a 150mm wafer).
Yeah,Tukwila is the biggest, but BTW, the original design of it is 30MB 8-T SRAM L3,NOW it only has 24MB
Now you can see what "limit" is
Speaking of chip manufacturing, is there a site that has a detailed step-by-step tour of some sort, pictorial or otherwise, that shows how making a modern integrated circuit works? Like, from creating the actual masks all the way through to finished product?
I've only read general descriptions, all the finer details elude me like how all the metal wires are applied, how layers are actually made and so on... It would be interesting to finally bring some clarity into all of that.
I've only read general descriptions, all the finer details elude me like how all the metal wires are applied, how layers are actually made and so on... It would be interesting to finally bring some clarity into all of that.
Speaking of chip manufacturing, is there a site that has a detailed step-by-step tour of some sort, pictorial or otherwise, that shows how making a modern integrated circuit works? Like, from creating the actual masks all the way through to finished product?
I've only read general descriptions, all the finer details elude me like how all the metal wires are applied, how layers are actually made and so on... It would be interesting to finally bring some clarity into all of that.
I thought intel has some great video's on their site. I'll go dig that up.
edit: Here's the PDF : http://download.intel.com/pressroom/kits/chipmaking/Making_of_a_Chip.pdf
inside it you will find links to a narrated animation of said slides.
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