Market Changes : ATi , nVIDIA , 3DLabs & SiS Rearangeing

[David G.]

I guess that you've all seen the last digitimes article which was saying that ATi increased it's shipements by 10% and that that it's exactly a market share increase .
Doing the calculations and considering that ATi curently owns 23 % of the market we can understand that it's share grew by 2.3% up to almost 26% .
That's not at all such a big increase but considering that it has been acomplished during the worst period of the year and that the situation this year is much worse than in the last 2 years I think it's very good .

In fall the shipements shold go back to normal ... meaning double the this period or even more . Also considering that ATi has now a marketing advantage from Radeon 9700 I think that ATi will regaing around 7 or 8 % of the market share in nVIDIA's dissadvantage .

Now I say that the TSMC move is logical . TSMC has been having problems with 0.13 micron technology for a long time now and nVIDIA needs a potent production line .
I think that nVIDIA will become a big UMC client in the next half of the year . UMC has a better 0.13 manufacturing process . Why ? Because it's because of UMC'c technology that the AMD AThlon CPUs will go up to 2000 Mhz and beyond . This make it clear that UMC has a good and viable 0.13 u process .

nVIDIA said it will switch it's whole line of cards over to 0.13 micron and it sure won'd be with TSMC's help . Those 24% let for TSMC represent the 0.15 and 0.18 micron chips .

nVIDIA will use UMC for the production of it's 0.13 chips .

SiS has it's own fab for Xabre and Xabre II and although the Xabre line isn't too much of a evolution step it still has the role as Radeon 9000 has , of bringing DX8.1 to the masses .

3Dlabs may be the third competitor on the gaming market ( I don't consider Matrox's Parhelia capable of competing with R300 or NV30 ) . But that's for Creative to decide and I hope that they won't overload the mid and low end market too as we need a radeon 9700 competitor to pull down the prices .
And they have a chance too as the weakest card from their range is as fast as a Radeon 8500 atlhough that test was done on an alpha card with beta drivers . The fastest card is practicaly 50% faster than that setup and considering that the P10 is a full programable chip I think drivers will help too , remember that P10 is the first OpenGL 2.0 card and it's build by the OpenGL creators .

 

[Tahir2]

UMC has a better 0.13 manufacturing process

Pure speculation on your part.

I have heard the opposite - but that is pure speculation too.

The AMD chip is a 37million transistor part - not really to be compared with a 120+ million chip.

 

[CosmoKramer]

The AMD chip is a 37million transistor part

Barton will have more transistors than that.

 

[Tahir2]

If AMD do not add SSE2 support or change the core (like improving the branch predictor) the Barton core will of course be:

37million transistors + additional 256KB L2 cache (dont know how many transistors that is).

Obviously it will be a lot lower than 120+ million transistors though.
Some of the moves away from TSMC are political as well as problems with poor yields etc.

 

[Nexus]

UMC has a better 0.13 manufacturing process

Pure speculation on your part.

I have heard the opposite - but that is pure speculation too.

Fact is that AMD expects to get the first UMC produced Athlons early next year. (http://www.eetimes.com/semi/news/OEG20020417S0077)

The AMD chip is a 37million transistor part - not really to be compared with a 120+ million chip.

And also note that the logic/memory ratio on a CPU with its big caches is much higher and logic is trickier to produce than memory.

 

[WaltC]

UMC has a better 0.13 manufacturing process

Pure speculation on your part.

I have heard the opposite - but that is pure speculation too.

The AMD chip is a 37million transistor part - not really to be compared with a 120+ million chip.

That's really the key question, I think: "How far ahead of current manufacturing processes is nVidia's nv30 design?"

I can only think nVidia would part company with TSMC only in the case of extreme barriers to their relationship, such as the FAB telling nVidia flato out that there's no way they could produce that chip this year. So will UMC fare any better? It seems they are promising nVidia they can in order to get the business, but will they run into the same roadblocks that TSMC has hit?

If they do, and if TSMC is unable to produce the chip this year, the nv30 could be delayed indefinitely. In that case I think we'd see nVidia substitute a less complex chip design and release it this year in the place of nV30--say the "nv28" or something.

 

[Nexus]

If AMD do not add SSE2 support or change the core (like improving the branch predictor)

In the AMD Hammer video the chewing gum chewing AMD guy said Barton will have just 256KB more L2.

the Barton core will of course be:

37million transistors + additional 256KB L2 cache (dont know how many transistors that is).

Barton should have about 54 million, while the core without L1 and L2 has only ~11 million.

It's sad that there are not more of such details about modern G/VPU caches and architecture publically known. It's interesting that compared to the CPU world such things are not common in the GPU marketing world.

 

[jjayb]

http://finance.yahoo.com/q?s=NVDA&d=t

Nvidia shares are now at $9.35.

Wish I had the money to buy some.

 

[Tahir2]

Is it true that NVIDIA expected TSMC to be .13 technology ready last year at the time of GF4?

 

[Nexus]

That's really the key question, I think: "How far ahead of current manufacturing processes is nVidia's nv30 design?"

NV30 isn't ahead of any manufactoring process, it is just that nVidias expectations with regards to yields/performance/price where probably long not met by TSMC.

For example, IBM produces its Power4 chip monster with 170 million transistors on an in-house 0.18 SOI copper process and they have it running at 1.3 GHz.

 

[Dave Baumann]

Is it true that NVIDIA expected TSMC to be .13 technology ready last year at the time of GF4?

Well, if you look historically then most of NVIDIA's products have been met with a new silicon process, up until GF4 - I think is reasonable to assume they had thought it would be ready by that point. I am still firmly of the opinion that they had intially pegged NV2A (XBox) for .13um as well, and when they realised it wasn't going to happen and they had to go for .15um was when the climbdown in speed occured (300Mhz->250MHz projected->233Mhz yeild).

 

[David G.]

If AMD do not add SSE2 support or change the core (like improving the branch predictor) the Barton core will of course be:

37million transistors + additional 256KB L2 cache (dont know how many transistors that is).

Obviously it will be a lot lower than 120+ million transistors though.
Some of the moves away from TSMC are political as well as problems with poor yields etc.

256 Kb cache is a lot of transistors .... don't know exactly but it's more than 10 mil ....

Don't make a confusion and start comparing CPUs to GPUs or VPUs . Sure a VPU like NV30 will have more than twice the transistor number but it is scaled at over 500% slower speed than a 2000 Mhz CPU .

Also ... baring in mind that it is possible that NV30 could have an external T&L unit we can understand that those 120 mil transistors could compose 2 different chips which could be cooled separately .

 

[Nagorak]

What exactly is the benefit to having a hard-wired TnL unit? Considering the R300 has 116 million transistors or so according to the latest account, I really hope the NV30 does not have a separate TnL unit or it's going to mean the rest of the chip which will matter in coming years will actually have less transistors than R300.

Then again, more transistors don't necessarily mean a better chip.

Edit: Maybe I misunderstood what you were saying, just that the TnL would be on a separate chip. Honestly that doesn't sound like much of a step in the right direction either. Maybe you can get better yields out of 2 smaller chips, but it seems like the whole off-die connection between them would bog the whole thing down. I guess you could cool them separately too, which would be a benefit...still it doesn't sound like the approach makes a lot of sense.

Of course if there were two different chips that would explain why Nvidia's CEO said the Nv30 had taped out back in June (or whenever) but now claims it has not. Maybe one chip has and the other hasn't. Kind of seems unlikely though and I probably shouldn't even have mentioned it since it will just fan the "tapeout" firestorm.

 

[Entropy]

256 Kb cache is a lot of transistors .... don't know exactly but it's more than 10 mil ....

Assuming that they will use a 6T design for their SRAM cells, 256KB cache should require 256k times 8 times 6 - roughly 12million transistors, plus pocket change.

But the you really can't compare the two by transistor count and use that as the sole yardstick of complexity.

Entropy

 

[OpenGL guy]

It's sad that there are not more of such details about modern G/VPU caches and architecture publically known. It's interesting that compared to the CPU world such things are not common in the GPU marketing world.

Mostly because it's very design dependent. How large your caches and FIFOs are, depends on many different factors and really aren't comparable between architectures. For example, a chip with multiple TMUs would probably want to have more texture cache than the same design with a single TMU, but that doesn't necessarily make a different design with less texture cache less efficient.

 

[Nexus]

256 Kb cache is a lot of transistors .... don't know exactly but it's more than 10 mil ....

Assuming that they will use a 6T design for their SRAM cells, 256KB cache should require 256k times 8 times 6 - roughly 12million transistors, plus pocket change.

If you look at the transistor counts of Palamino and Morgan and their different cache sizes its clear they use 8T for their L2, which would be 16,4 million for 256KB.

 

[Nexus]

It's sad that there are not more of such details about modern G/VPU caches and architecture publically known. It's interesting that compared to the CPU world such things are not common in the GPU marketing world.

Mostly because it's very design dependent. How large your caches and FIFOs are, depends on many different factors and really aren't comparable between architectures. For example, a chip with multiple TMUs would probably want to have more texture cache than the same design with a single TMU, but that doesn't necessarily make a different design with less texture cache less efficient.

Certainly. But that is mostly the same in the CPU world. Pentium 4's, AthlonXP's, Crusoe's and Itanium's caches differ and must be seen in the architectural context, direct comparisons are pretty useless if you don't take into account the architecture they must assist. You simply need to know all details of the hardware design to analyse it.

I believe the architectural secrecy in the G/VPU world is because there is (from their viewpoint) no need for it, their bare hardware is not exposed to programmers, you only communicate through the driver. Competition is probably also a big point, there are still very differing implementations, much they could "learn" from each other.

How much G/VPU architecture talk would there be if they would make design/architecture details and even "errata" public like Intel and AMD..

 

[David G.]

Edit: Maybe I misunderstood what you were saying, just that the TnL would be on a separate chip. Honestly that doesn't sound like much of a step in the right direction either. Maybe you can get better yields out of 2 smaller chips, but it seems like the whole off-die connection between them would bog the whole thing down. I guess you could cool them separately too, which would be a benefit...still it doesn't sound like the approach makes a lot of sense.

Sure making the conection dependent on the PCB could be a problem but I think it's not that difcult to go over it . See how SIS has it's chipset interconect @ 1,2Gb/s ....

 

[asicnewbie]

NV30 isn't ahead of any manufactoring process, it is just that nVidias expectations with regards to yields/performance/price where probably long not met by TSMC.

For example, IBM produces its Power4 chip monster with 170 million transistors on an in-house 0.18 SOI copper process and they have it running at 1.3 GHz.

I'm not sure that's a fair comparison.

IBM (like Intel) tweaks its foundry-lines (which produce CPUs) specifically for its own products. Technology-wise, other merchant foundries (TSMC/UMC/Chartered/etc.) suffer from having to serve "the lowest common denominator." I.e., they have to generalize their ASIC product-line for a 'general' market. From a customer's standpoint, IBM's 'superior foundry technology' comes at the expense of design flexibility -- "third-party" layout/physical-circuit design tools don't exist for IBM's most advanced foundries, and you're stuck with using IBM's supplied tools, or putting your trust in IBM's backend-services to finish-up your work.

Equally important, IBM (and TI, LSI, etc.) charge 2.0X or more (per fabbed wafer) for an equivalent digital-logic manufacturing process (0.13, 0.18, 0.25, etc.) than TSMC/UMC.

From a business standpoint, IBM makes a lot more money (per wafer) by selling packaged CPUs than selling fabbed-wafers to other companies. During capacity crunches (or yield problems), IBM therefore prioritizes its internal CPU business at the expense of foundry customers. I don't know whether IBM has actually kicked a paying customer, but the possibility of this happening is on every potential customer's mind. (To a lesser extent, LSI's foundry operation suffers from the same situation. Strangely, LSI has contracted TSMC to fab customer chips!)

As a result of all this, IBM's foundry customers are limited to relatively few companies (Xilinx immediately comes to mind) who absolutely need exotic technologies or have a past relationship with IBM. (Xilinx's Virtex2-Pro FPGAs integrate embedded PowerPC CPUs on each FPGA.)

My speculation is that NVidia probably evaluated IBM's ASIC foundries and decided a slightly less advanced manufacturing process (and much lower per-die cost) formed a better strategy. Likewise, ATI, 3DFX, 3Dlabs, S3, Trident all picked UMC or TSMC as their foundries.

 

[David G.]

I was wondering in some post around these forums if I should mention Trident as a new , true player om the 3D market ...

After seing what Anand said about their chip I guess that Trident will enter strongly in the battle . Even if the 80% of GF4 standard is not met , I think the cards will be faster than SiS's Xabre and that only Xabre II would change the picture .

Now .... who's the manufacturer for Trident chips ? UMC . UMC is to make 0.13 XP4 chips , UMC is to make 0.13 Bartons .... I'm pretty sure that UMC is the one that will manufacture NV30 chips too .