By most accounts, the 0.13-micron process technology node has been a major disappointment. Despite having had more than a year to work out the glitches, the chip and EDA industries are still grappling with low yields and false wafer starts caused by poor signal integrity, botched attempts at integrating new materials and an exceedingly high degree of in-die and in-wafer slop.
At 0.13 micron, for example, there are more interactions between libraries on the same rows and those on different rows. That's one reason it's taking an unacceptably long time to reach post-tapeout fabrication, said Mark Lavin of IBM's T.J. Watson Research Center
