Interesting stats on nVidia engineering

[watupwidat]

http://www.eedesign.com/story/OEG20020612S0051

Specifically on GF4 project:

63 million transistors, 78% logic

50% of RTL from GF3 modified

400k lines C , 800k lines Verilog

Schedule targets: 9 months (!!) to tapeout, 100 days from tapeout to ramp

40 to 70 engineers in implementation alone

$160 million in tools, $40 million of which on emulation





Wow, $160 million can probably buy a whole lot of copies of MS Paint.

 

[RussSchultz]

9 months isn't terribly long for such an extensive project.

100 days from tapeout to ramp is pretty astoundingly short.

 

[ben6]

Yep saw that in our Ti4600 presentation at Geforce4 launch . Pretty fast work

 

[Mintmaster]

9 months isn't terribly long for such an extensive project.

100 days from tapeout to ramp is pretty astoundingly short.

I think he thought the 9 months was very short, as do I. But then again, it isn't a huge difference from GF3.

100 days isn't that astounding, but it is rather fast. I think 4-5 months is average, so 3.3 months is fast but not mind blowing.

 

[watupwidat]

That's fast by most anyone's standards regardless of the size of the change from GF3 to GF4.

That's a well oiled sweat shop that Jen-Hsun is running up there in Santa Clara.

 

[mboeller]

http://www.eedesign.com/story/OEG20020612S0051

Specifically on GF4 project:

63 million transistors, 78% logic

78% logic => 22% Cache (??)

this would mean 13,86 Mio transistors for SRAM. With 6transistors per bit ( 4transistors per bit would
be possible too ) => 2,3Mbit SRAM or ~ 282KB Cache



nice info if correct.

 

[Simon F]

78% logic => 22% Cache (??)

It probably includes other buffers etc that use SRAM blocks, not just a (texture) cache. Program storage (VS/PS) , vertex buffering, etc, springs to mind.

 

[Dave B(TotalVR)]

Simon, I was just wondering. We keep seeing the silicon maps from other chips, like whenever a new cpu comes out you have people posting the magnified picture of the silicon saying 'this are is the FPU units and this bit is the memory controller'. We've seen it for some graphics cards too, is that information deliberately kept secret in the case of PowerVR though?

In other words, would we be able to see such a map if we asked IMGTEC?

The reason I ask is that I was wondering just how much die space the tiling aspect of the chip takes up.

Dave

 

[Simon F]

Dave,
The only graphics chip I ever recall seeing labelled that way was the one in the GameCube. Speaking personally, it doesn't appear to be graphics IHVs' policy to publish the innards.

Simon

 

[Glonk]

The GeForce 4 has a similar type of diagram: http://www.tomshardware.com/graphic/02q1/020206/geforce4-02.html

 

[Kristof]

The GeForce 4 has a similar type of diagram: http://www.tomshardware.com/graphic/02q1/020206/geforce4-02.html

That might be any kind of chip with an overlay of the main blocks of that GPU...

 

[Ailuros]

Dave,
The only graphics chip I ever recall seeing labelled that way was the one in the GameCube. Speaking personally, it doesn't appear to be graphics IHVs' policy to publish the innards.

Simon

We users are "nosy" and you know it

 

[ram]

Here is another one, guess what chip it "is"

 

[Pete]

I wonder if he used Paint or Corel Draw for that?

 

[Typedef Enum]