Tensilica Tackles Bottlenecks
Tom R. Halfhill - Senior Editor {05/31/2004}
Rarely has the ascendance of embedded processors been more evident than at the recent Embedded Processor Forum, where several companies announced products and features that must seem like tantalizing fantasies to the architects of staid PC processors. One company in particular, Tensilica, is continuing to pursue a farsighted corporate vision of architectural flexibility and automated design.
At EPF 2004, Tensilica announced new versions of its configurable microprocessor core and optional DSP engine, which are licensed as soft intellectual property (IP). When combined with the company’s previously announced VLIW-like instruction extensions and next-generation development tools, they will redefine the possibilities for embedded processors.
The new Xtensa LX is a major upgrade of Tensilica’s existing configurable processor core, the Xtensa V. Xtensa LX tackles three challenges vexing today’s CPU architects: the architectural limitations on compute efficiency, the bottlenecks on I/O bandwidth, and rising power consumption. For SoC developers, Xtensa LX preserves the advantages of a customizable CPU architecture while laying the groundwork for future development tools that will further automate the task of creating an optimized SoC design.
Tensilica also announced at EPF a new configurable DSP engine called Vectra LX. Designed specifically for the Xtensa LX processor—Tensilica already offers a DSP engine for earlier Xtensa cores—Vectra LX uses 64-bit instruction words containing three issue slots for ALU, multiply-accumulate, and load/store operations. In all, Vectra LX supports about 200 instructions for 16-bit fixed-point signal processing. Vectra LX is included with Xtensa LX and adds a level of DSP performance unprecedented in a synthesizable RISC processor.
All this probably seems too good to be true. However, Tensilica can back up its claims with independently certified benchmark results. Xtensa LX clobbers every other benchmarked processor in its class—and even some processors out of its class. For instance, in the EEMBC consumer suite, Xtensa LX achieved the highest out-of-the-box ConsumerMark score ever recorded by a licensable CPU core: 171.6 when simulated at 330MHz. That’s more than three times higher than the previous out-of-the-box champ, the Philips TriMedia TM5250, which scored a ConsumerMark of 51.3 when simulated at 500MHz.
Tensilica also submitted Xtensa LX to Berkeley Design Technology Inc. for DSP benchmarking. Result: an optimized Xtensa LX core and Vectra LX DSP engine, simulated at 370MHz, easily outran every other licensable DSP or CPU core ever tested by BDTI. Xtensa LX scored a BDTIsimMark2000 of 6,150—about 70% higher than the previous champ, the CEVA-X1620 DSP, which was simulated at 450MHz.
To achieve these extraordinary benchmark results with a small RISC processor, Tensilica has introduced some groundbreaking new technology and development tools. We believe it’s only a matter of time before Tensilica’s approach to configurability and design automation exerts more influence over the whole industry.
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