Clockless Core
- Thread starter epicstruggle
- Start date
Clockless chips have existed in the past too, they never amounted to much.
Besides, without a reference signal, how does the chip vendor guarantee a certain performance level on the product they sell? I assume there has to be a clock signal fed into the thing at some stage or another in the instruction pipeline or it'd be like buying something completely unknown. Nobody would accept that...
Besides, without a reference signal, how does the chip vendor guarantee a certain performance level on the product they sell? I assume there has to be a clock signal fed into the thing at some stage or another in the instruction pipeline or it'd be like buying something completely unknown. Nobody would accept that...
Clockless means that data propagation throughout the core isn't determined by any sort of clock signal. Instead, you allow the signal propagate through a pipeline from start to finish as fast as the transistors will switch. This allows the performance of a processor to scale as the average of the switching speeds of the transistors, instead of scaling as the slowest switching speed.
As we move to smaller and smaller processes, the spread in relative switching speeds among transistors becomes much larger, which tilts things in favor of the clockless processor.
Anyway, here's Wikipedia's article on it:
http://en.wikipedia.org/wiki/Clockless_processor
Edit:
Oh, and here's another link:
http://research.sun.com/features/async/
I really think that asynchronous circuits are the future, provided we don't move away from silicon too terribly soon
As we move to smaller and smaller processes, the spread in relative switching speeds among transistors becomes much larger, which tilts things in favor of the clockless processor.
Anyway, here's Wikipedia's article on it:
http://en.wikipedia.org/wiki/Clockless_processor
Edit:
Oh, and here's another link:
http://research.sun.com/features/async/
I really think that asynchronous circuits are the future, provided we don't move away from silicon too terribly soon
Guden Oden said:
They are self-timed internally. They go faster the higher supply voltage they get.
Synchronous processors are binned by max operating frequency and power consumption
Asynchronous processors are only binned by power consumption (ie. a certain level of performance has to be reached at a certain power level to go into a specific bin)
The University that I went to was involved in the development of an asynchronous DSP for hearing aids back in 1995. They ended up with an order of magnitude performance/watt advantage compared to off the shelf DSPs.
Cheers
Unfortunately, there's a huge amount of work that needs to be done before clockless processors are ready to go up against larger chips. While they apparently can lead to order of magnitude increases in performance, it's going to take a whole lot of work to get the development tools close to those currently available for clocked processors.
Since they're apparently making inroads into some niche corners of the industry, it's my hope that there will be a market for the development of the technology which will lead to the development of these tools.
Since they're apparently making inroads into some niche corners of the industry, it's my hope that there will be a market for the development of the technology which will lead to the development of these tools.
Wasn't the last alpha chip partially async as well? The other area they are great at is reduce noise from EM since it will be broad spectrum. I really think the future in silicon in 3D async chips with high k dielectrics i.e. Super pararrelised extremely power efficent chips.
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Fruitfrenzy
Newcomer
It sounds like a complete nightmare to test and debug relative to a normal clocked processor. It must be very difficult to be sure that your design is complete.
How can you be sure that your logic can cope with any combination of relative speeds between the huge number of transistors in your design?
How can you be sure that your logic can cope with any combination of relative speeds between the huge number of transistors in your design?
That's more a problem with current processors than it is with asynchronous designs.Fruitfrenzy said:
And besides, think about it: any time you have parallel execution, the execution times of the various threads are unknown, because you typically cannot know ahead of time whether or not there will be cache hits for all requested memory accesses. This doesn't change things any, and opens the way to potentially more elegant solutions.
Fruitfrenzy
Newcomer
Chalnoth said:
Can you explain why you think that? At least with a synchronous design there are a finite number of possibilities in terms of relative timings of two paths.
It seems to me that asychronous logic would require more signals being routed about to signal when each bit of data is ready. I suppose you have valid-enable type signalling with synchronous logic as well but it some cases assumptions can be made that a particular result will be ready after n clocks. That kind of assumption will never be safe in asychronous cases.
The transistors still have different switching speeds in synchronous designs. So when the wrong thing takes a little bit too long, the whole chip crashes. This isn't a problem with asynchronous designs.Fruitfrenzy said:
I don't think this is as much of a problem as pipelining for asynchronous designs. If you want to maximize processing power, you want to send that next instruction as quickly as possible, but you don't want it to collide with the previous or next instructions, if those instructions take different paths through the logic to the end result.
But just syncing the outputs, I think that's basically a solved problem.
MulciberXP
Regular
wow, i totally misread the title of this thread
it seems this company also has clockless processors as far as I understand it:
http://www.intellasys.net/products/index.php
By the way this are the "famous" Sea of Processors "CPUs" from Chuck "Forth" Moore.
http://www.intellasys.net/products/index.php
By the way this are the "famous" Sea of Processors "CPUs" from Chuck "Forth" Moore.
Fruitfrenzy
Newcomer
Chalnoth said:
Which is why when a design is layed out etc it is done with a specific silicon process in mind and a specific range of swithcing speeds. Each functional block is designed to allow for the slowest likely transistor speed so in most cases the assumption that a result will be ready is safe.
That will be where the performance increase in asynchronous logic comes from but I still think it will come at the cost of increased complexity. If you think about it, if it was easy everyone would be doing it.
I don't think it will come at an increase in complexity, though. It's harder to design asynchronous processors to be sure, but it should reduce many types of complexity. For example, if you want to have a fast processor, you need every single pipeline stage to be of very nearly the same length. This is a hard problem to solve, and you also need to store intermediate values at the end of every pipeline stage.
With an asynchronous design, this whole paradigm is turned on its ear, as you don't need to worry about pipelining in the normal sense.
I think that the primary problem is just that we haven't spent nearly as much engineering time working on asynchronous designs, so that it will take a long time to get anything but the smallest asynchronous processors up to par with today's synchronous designs.
With an asynchronous design, this whole paradigm is turned on its ear, as you don't need to worry about pipelining in the normal sense.
I think that the primary problem is just that we haven't spent nearly as much engineering time working on asynchronous designs, so that it will take a long time to get anything but the smallest asynchronous processors up to par with today's synchronous designs.