XDR2 to quintuple memory data transfer speeds by 2007
By Scott Fulton
July 7, 2005 - 10:45 EST
Los Altos (CA) - "Parallelism" is the keyword underscoring several semiconductor architectures this decade. Now it's the turn of the memory: Rambus announced the availability of "micro-threading" for XDR2 memory, the company's next generation memory technology. Memory clock speeds will catapult to 8 GHz, up from a current maximum of 4.8 GHz of XDR1.
"The bandwidth requirements of game platforms and graphical applications have been growing exponentially," Steven Woo, Rambus' senior principal engineer at Rambus, told Tom's Hardware Guide. "About every five or six years, it goes up by a factor of 10. PlayStation 3, for example, will have a memory bandwidth capability of 50 GByte per second." If this trend continues, projected Woo, a theoretical 2010 model "PlayStation 4" could require ten times the memory bandwidth as next year's PlayStation 3. A statistical projection made in 2004 by NVIDIA's Vice President of Technical MarketingTony Tamasi-- cited by Woo--anticipates that a top-of-the-line 3D game could conceivably require memory bandwidth of 3 TByte per second.
To begin addressing this staggering upward slope to which NVIDIA and others are pointing, Rambus unveiled XDR2, with a range of added and enhanced technologies, including the company's new simultaneous data throughput concept, micro-threading.
As Woo demonstrated exclusively for Tom's Hardware Guide, micro-threading was designed to address a growing problem brought on by the very 10x bandwidth factor that's revolutionizing the memory industry today: a growing mismatch between the memory interface frequency and the core signaling rate. As interfaces such as Rambus' XIO core for XDR increase in speed, while at the same time core signaling rates increase by a lesser rate or not at all, the amount of data that a controller must fetch for each clock cycle rises proportionately with the gap between these two speeds. A feature that was already integrated in first generation XDR coordinates memory interface frequency and the core signaling rate.
Another problem in modern memory technologies is the increasing byte-size of data pieces that can be accessed. This loss of "granularity" actually results in performance degradation, especially with graphics cards that require rapid access to smaller and smaller triangles to achieve true high-definition rendering. Micro-threading addresses this problem, stated Woo, first by recognizing that DRAM technology divides banks of data elements into halves or quadrants, and next by developing a technique by which those quadrants can be addressed both independently and simultaneously. No bandwidth is lost, but access granularity is theoretically divided by four, at the expense of a "small" increase to the number of commands required to access data within the independent quadrants, according to a Rambus white paper.
The payoff may come in the form of capabilities for future graphics cards to establish very deep, very narrow look-ahead pipelines for very small triangles, which could lead to another huge performance boost for scene rendering. "Those pipelines are so incredibly deep," said Woo, "that you have lots of visibility way ahead of time as to where the triangles are, and where they're going to be accessed from."
