AMD K8L - this is not a tweaked K8 ...

C

chavvdarrr

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http://www.realworldtech.com/forums/index.cfm?action=detail&id=67239&threadid=67239&roomid=11
Name: David Kanter (dkanter@realworldtech.com) 5/16/06

Hey Guys,

I'm sitting in a keynote from AMD's Chuck Moore, and here is information on the next generation i.e. K8L.

0. Native quad core
1. Hypertransport up to 5.2GT/s
2. Better coherency
3. Private L2, shared L3 cache that scales up.
4. Separate power planes and pstates for north bridge and CPU
5. 128b FPUs - see 14,15
6. 48b virtual/physical addressing and 1GB pages
7. Support for DDR2, eventually DDR3
8. Support for FBD1 and 2 eventually
9. I/O virtualization and nested page tables
10. Memory mirroring, data poisoning, HT retry protocol support
11. 32B instead of 16B ifetch
12. Indirect branch predictors
13. OOO load execution - similar to memory disambiguation
14. 2x 128b SSE units
15. 2x 128b SSE LDs/cycle
16. Several new instructions

Coprocessors:
media processing
JVM/CLR acceleration
TOE, XML or SSL processing

Anyway, ours news posting is somewhat broken, so I might not get to turn this into news. But you heard it here first : )

DK
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Seems like good Conroe competition - ~ same FPU raw power, 128-bit L1 data access, shared L3 cache, HT3.0 with up-to 40GB/s (5G transfers), also note points 12 and 13 ;)

And seems like very good chip for servers ... and VERY small - 150mm2 being quad core! - dual core Conroe at 65nm is 140mm2
 
Possibly. I'd like to know more about what "L3 cache that scales up" means. Cache size could potentially be another way to differentiate between the server/HPC and consumer markets.
 
Is the L3 on-die? I thought it was something that is on the mobo itself. Perhaps there is some on the chip, with expandable meaning that there are different configs available on the mobo side of things.

:?:
 
radeonic2 said:
so what about us consumers.. what do we get :???:
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Within a month or two. Windsor (dual) and Orleans (single). DDR2 memory support with Pacifica and Presidio technologies. Late 2007 looks to be modified architecture, DDR3 support, dual and quad core line ups some of which will contain L3 cache, I/O virtualization and support for RAID 5 (Opterons). We may see AMD FX parts break 3.4GHz.

In otherwords, nothing new and interesting for quite a while. Dont forget they have yet to break from 90nm which will be the main goal this year, getting production primarily to 65nm.

Expect Intel to have DDR3 and 1333FSB Dual core chips this time next year and quad core on the way as well. There is some speculation that the Extremely Expensive or EE edition of Conroe may be distinguished by a 1333FSB.

Then in 2008 or 2009 Intel will be releasing desktop parts with their own onboard memory controllers.
 
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SugarCoat said:
Then in 2008 or 2009 Intel will be releasing desktop parts with their own onboard memory controllers.
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no kidding?! onboard memory controllers? maybe on-chip?

yet, i had read somewhere that " separated memory controllers controllers give more flexibility and are not slower" ... :D
:devilish:
 
Yup, unless Intel is just spreading the FUD around, they seem to be rather against on-chip memory controllers at the moment.
 
... and preaching that glueing 2 separate chips into one, sharing the bus is not a problem...

same tactics as NV vs Ati at NV30 era ("who cares about DX9?") and as Ati vs NV at X800 era ("who cares about SM3.0?") ... until you have the feat, downplay it ... :D
 
Actually incorporating memory controller is not necessarily a good move in server market. For example, the biggest problem with Opteron is its (lacking of) memory RAS. For smallish servers, memory RAS is not that important. However, it limited the possibility of Opteron for higher-end servers. On the other hand, it's quite possible to provide very nice memory RAS for Xeon platforms, such as IBM's X3.

Of course, for AMD's target market, Opteron does not really need that kind of memory RAS. However, after the initial success of Opteron, AMD needs to put something better into Opteron for higher-end markets, thus the better memory RAS for K8L. Of course it's still not in the same level of X3.
 
chavvdarrr said:
no kidding?! onboard memory controllers? maybe on-chip?

yet, i had read somewhere that " separated memory controllers controllers give more flexibility and are not slower" ... :D
:devilish:
Click to expand...


Yes, excuse the typo. It will be a quad core design featuring the on die memory controller, first of such kind is codenamed Tukwila. Desipite what you think Intel's current stance is Chalnoth, please note i did specifically say 2008/2009. Snoop around if you like.


edit, save ya the trouble.

http://www.realworldtech.com/page.cfm?NewsID=361&date=05-05-2006#361

I dont find it entirely impossible they may be dedicated to on die controllers by 2009 as memory speeds get faster. On die controllers should have considerable advantage at the DDR3/DDR4 speeds over the current way.
 
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SugarCoat said:
Yes, excuse the typo. It will be a quad core design featuring the on die memory controller, codename is Tukwila. Desipite what you think Intel's current stance is Chalnoth, please note i did specifically say 2008/2009.http://www.realworldtech.com/page.cfm?NewsID=361&date=05-05-2006#361
Click to expand...

:???: Huh? Tukwila isn't a desktop part and never will be (it's an Itanium!). The interesting news about Tukwila is that it sits on CSI, which will also be introduced for Xeons around that time AFAIK. When (if!) CSI will make it to the desktop... is anyone's guess I think.
 
pcchen said:
Of course, for AMD's target market, Opteron does not really need that kind of memory RAS. However, after the initial success of Opteron, AMD needs to put something better into Opteron for higher-end markets, thus the better memory RAS for K8L. Of course it's still not in the same level of X3.
Click to expand...
What do you mean by better RAS in this situation?
 
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