Stacked DRAM is poised to be integrated in the memory hierarchy of both CPUs and GPUs. Die-stacking has significantly improved performance and bandwidth of DRAM, making it suitable to be used as last level cache.
Our TPDS 2015 paper "A Survey Of Techniques for Architecting DRAM Caches" reviews techniques for designing DRAM caches.
Part of the abstract: In face of increasing cache capacity demands, researchers have now explored DRAM, which was conventionally considered synonymous to main memory, for designing large last level caches. In this paper, we present a survey of techniques for architecting DRAM caches. Also, by classifying these techniques across several dimensions, we underscore their similarities and differences. We believe that this paper will be very helpful to researchers for gaining insights into the potential, tradeoffs and challenges of DRAM caches.
Our TPDS 2015 paper "A Survey Of Techniques for Architecting DRAM Caches" reviews techniques for designing DRAM caches.
Part of the abstract: In face of increasing cache capacity demands, researchers have now explored DRAM, which was conventionally considered synonymous to main memory, for designing large last level caches. In this paper, we present a survey of techniques for architecting DRAM caches. Also, by classifying these techniques across several dimensions, we underscore their similarities and differences. We believe that this paper will be very helpful to researchers for gaining insights into the potential, tradeoffs and challenges of DRAM caches.