32gflops for each APU?

[bbot]

How was this figure derived from reading the cell patent? I went back and read through the whole thing and can't find where it mention an actual performance figure for an APU. In fact , it said APUs can have different "speeds" and still work together. Did someone work backwards, assuming that the performance of the broadband engine will be 1 tflops, and derived the 32gflops figure for each APU from that?

 

[V3]

[0068] FIG. 4 illustrates the structure of an APU. APU 402 includes local memory 406, registers 410, four floating point units 412 and four integer units 414. Again, however, depending upon the processing power required, a greater or lesser number of floating points units 512 and integer units 414 can be employed. In a preferred embodiment, local memory 406 contains 128 kilobytes of storage, and the capacity of registers 410 is 128.times.128 bits. Floating point units 412 preferably operate at a speed of 32 billion floating point operations per second (32 GFLOPS), and integer units 414 preferably operate at a speed of 32 billion operations per second (32 GOPS).

 

[Paul]

Floating point units 412 preferably operate at a speed of 32 billion floating point operations per second (32 GFLOPS)

 

[Colourless]

Assuming each floating point pipeline can do 1 FMAD per clock then you'll get 8 flops per cycles. Then if you are running at 4 GHz you'll get 32 GFlops/second

 

[PC-Engine]

Assuming each floating point pipeline can do 1 FMAD per clock then you'll get 8 flops per cycles. Then if you are running at 4 GHz you'll get 32 GFlops/second

So if CELL runs at say 1 GHz it would be 8 GFLOPS per APU?

 

[London Geezer]

Assuming each floating point pipeline can do 1 FMAD per clock then you'll get 8 flops per cycles. Then if you are running at 4 GHz you'll get 32 GFlops/second

So if CELL runs at say 1 GHz it would be 8 GFLOPS per APU?

yep.

still skeptical about the 4GHz figure. almost as skeptical as pretty much EVERYTHING about PSP... but we'll just have to wait and see...