1T-SRAM memory modules for 3D cards? Matrox?

CoolAsAMoose

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First a question:

With NEC already producing discrete 1T-SRAM chips for the GameCube, I guess they could offer these at a reasonable price to manufacturers of 3D cards as well. Would the current and next-generation of 3D chips benefit from the low latency of 1T-SRAM?


Now some speculation:

Rumors say that Matrox Parhelia is using some different memory compared to the competition(??). Could it be 1T-SRAM?

Just a reminder: Matrox have used different memory from most other manufacturers before - namely WRAM (dual-ported, Windows-tailored) on the original Millenium. And NEC manufactured the G200 chip (not sure about G400) for Matrox, so Matrox and NEC have teamed up before.
 
Hrm without directly answering the question. I think it's unlikely we'll see 1T-SRAM in a card until the entire framebuffer can be economically placed on such memory. It's highly unlikely that a 128MB or more (all cards going forward for the high performance segment will likely have 128 or more) card would have this memory at this time ...
 
If anyone used 1T-SRAM in the near future, it'd be ATi - remember that they inherited a fully-functional 1T controller from ArtX.

And amount isn't that much of a problem AFAIK... GCN contains 24MB in two (small) chips. They could probably be expanded to 16MB/chip without too much difficulty, and with eight chips (standard), that's 128MB.

And actually, if they went with only 64MB external, they could probably get away with a small amount of embedded memory for Z-buffering, kinda like the Kyro II and Flipper, which would result in less external RAM needed.
 
Strangely enough, what I posted is what the head of the ArtX team at ATI told me at E3 last year. They said it would be a while before it happens without being specific
 
rumour read says

says it might use a small amount of embedded memory...heh who knows it could be 1-t sram/dram and then a pool of external memory
 
We have some nice views on the likelyness of seeing 1T-SRAM on graphics cards here, but I still have no answer on my original question: How much of a benefit would it be to have the low latency of 1T-SRAM as external memory on a 3D-card?

I'll try to answer the question myself, and waiting to be corrected: I guess that modern 3D chips with large on-chip caches and (intelligent) crossbar memory controllers can hide most of the latency of the external DDR-SDRAM. Also, todays "fixed-function" 3D graphics is not as vulnerable to latency as the CPU code with all its branches etc. Am I right? So having 1T-SRAM as main CPU memory (or UMA memory as in NGC) would be more beneficial!?!

But what about the upcoming, more programmable 3D chips: could they benefit more from low-latency external memory? The displacement mapping hardware of Parhelia maybe would like low latency!?!



And amount isn't that much of a problem AFAIK... GCN contains 24MB in two (small) chips. They could probably be expanded to 16MB/chip without too much difficulty, and with eight chips (standard), that's 128MB.

The main issue here is volume. The 12 MB chips are already produced in fairly big volumes for the NGC. So if NEC isn't already producing 16 MB chips for some other customer, the 12 MB would be the ones to use. 8 of those would give 96 MB.

I'm not sure, however, if the NGC 1T-SRAM chips are DDR. Anyone?



Strangely enough, what I posted is what the head of the ArtX team at ATI told me at E3 last year. They said it would be a while before it happens without being specific

E3 last year (May 2001) to R300 launch (Fall 2002?) is a "while" in this industry. Just a note.....
 
Hrm , there will be no 1T-SRAM on R300 . I believe they will use 128bit DDR or 256bit DDR .... I've been hearing weird rumors on the R300...
 
CoolAsAMoose said:
3:rd try: How much of an advantage would using low latency 1T-SRAM as (external) memory on 3D-cards be?

Not quite sure, but I think the advantage would be small. What generally happens in present-day 3d cards is that memory accesses for different pixels are overlapping to such an extent as to make memory bandwidth rather than latency the main bottleneck. Geforce3-style pixel shading doesn't seem to affect this situation much, and I don't think displacement mapping will either. It's a bit harder to tell what will happen in case of arbitrary programmability, but if you have 200+ processing units all hammering the memory bus at the same time, you could still very well overlap memory accesses to the point where you are limited by memory bandwidth and not memory latency.
 
Actually, now I can't say at all. No , I'm not under any kind of NDA if that's what you're thinking . But I did have a nice conversation with someone working on the chip, on some things and it would be inappropiate to give concrete information....
 
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