Yesterday reading on the motorola website I saw that the Altivec unit was created before of the PowerPC G4 (that is a PowerPC G3+Altivec Unit).
This Coprocessor that makes the works of a complete SIMD unit (4 integer ops/4 fp ops) only has 4 milions of transistors and was designed for be in all multimedia devices as a coprocessor (it needs the registers of a main PPC CPU).
If I take Altivec and I add some L2 cache is when the name APU comes to my mind.
Ergo, is possible to make a PowerPC CPU with 8 attached and linked APU (Altivec with L2 cache) and the number of transistors will be less than take the VU0 from EE and make a version with a better Integer ALU (upgrading from 16 bits to 128 bits SIMD).
¿This idea of mine could be a realistic roadmap for PS3 CPU?
This Coprocessor that makes the works of a complete SIMD unit (4 integer ops/4 fp ops) only has 4 milions of transistors and was designed for be in all multimedia devices as a coprocessor (it needs the registers of a main PPC CPU).
If I take Altivec and I add some L2 cache is when the name APU comes to my mind.
Ergo, is possible to make a PowerPC CPU with 8 attached and linked APU (Altivec with L2 cache) and the number of transistors will be less than take the VU0 from EE and make a version with a better Integer ALU (upgrading from 16 bits to 128 bits SIMD).
¿This idea of mine could be a realistic roadmap for PS3 CPU?