Recent content by Vhatt

Mr. Fox I remember that thread and I did ask a few questions in there as well. I did read through the memory thread but may have glossed over or misunderstood that for max possible bandwidth the memory sizes needed to be the same. Working it out now, the ideal memory size would be 500mb per...

ToTTenTranz your post a few pages back about the XSX memory was pretty clear but I have a correction or two and a suggestion for better bandwidth utilization and latency hiding. While I agree that there are 10 chips, the 10MB file should be split into 500kb partitions per channel (10 chips...

Guys, your recent discussion on memory contention lead me to do some googling to try and better understand what it was. While doing so I came across the following http://pages.cs.wisc.edu/~basu/isca_iommu_tutorial/IOMMU_TUTORIAL_ASPLOS_2016.pdf I think the bits that pertain to the next-gent...

The discussion on the CPU core caching for the XSX made me go back to a little counting I did on my own from the spec reveal. MS indicated that the total onboard cache for the XSX APU was 76mb of SRAM. I was curious as to how that would be broken down for the CPU & GPU so did some counting based...

I was going to ask this in the XSX memory thread but since it has now been closed I'll ask it here. 1. It was explained to me in the a.b.m. thread that GGD6 is not dual-ported and that each channel addresses half of the chip. In searching for the information myself I came across this...

Please correct me if I'm wrong but GDDR6 chips are dual channel (ported) and allow for synchronous data transfers (just like the ESRAM in the Xone?). The GPU only gets 10gb at the full 560GB when both channels are used and the CPU can only access one channel of the larger chips with the other...

I believe this explanation by Urian @ Dustruptive Ludens gives a clear explanation of what may be happening with XSX memory http://disruptiveludens.com/ps5-y-xsx-gddr6-y-acceso-a-memoria (google translate as needed). I'm a bit curious as to what MS has done with the on-chip SRAM as they felt...

Hello all, I have a question regards the NVME ssd solution in the XSX. Do you think MS would have included the ability to double the ssd bandwidth to the system when the 2nd ssd is plugged in? I am thinking something along the lines of RAID0. Would a feature like that be more cost-effective than...