Recent content by Urian

48 or 49 bits of adressing.

Am I the only one who sees an almost Tile Renderer?

And I forgot something to add... I never said in my blog post that the Super-SIMD only would give the hability for Real Time Raytracing. I made clear in it that Traversal Unit/RT Cores would be needed. In my blog post I talk about the possibility of AMD adding some of the AI accelerators from...

I am the one who made the original article that reddit linked. I made clear in my own article that I could be wrong at 100% and this is a speculation with the few info that we have. Since is only partially informed speculation I am not going to add anything or say anything about it.

Then... Write them.

In Raven Ridge Slides is clear that the coherent part of the uncore (of course in Raven Ridge all the access is coherent) takes memory clock*32 bytes of bandwidth. Wel,,, the last rumor of Navi talks about how the GDDR6 speed is 12.8 Gbps and we have the rumor that PS5 GPU runs at 1.8 Ghz, of...

Sorry.. I forgot to put the link to the paper.

Well... AMD has a CU with traversal units since... Hawaii.

Is this possible for the Next Gen? Thanks for your time.

Thanks for the feedback. I plan to update the diagram correcting it and changing with the new info.

From what I understand from the original patent the answer is no.

(Core Alu+Side ALU)+Side ALU=Full ALU+Side ALU. In other words, physically you have 2 Side ALUs+1 Core ALU but 1 Side ALU+Core Core ALU runs as a "Full" ALU.

CAKE means Coherent AMD socKet Extender. And well... I decided to make an speculation in form of diagram of the Super-SIMD unit. I am sure that is wrong but this is what I understood reading the last patents.

Well... The diagram is simplified in the CU part where I believe that the Super SIMD patent is going to be applied. The result could be a Volta/Turing like CU where the ALUs could be used in traditional way or as tensor cores.

I was bored.