Recent content by Unwinder

That's not the case, Chris. It is not just a software 2D/3D clock switching technology, which was available for years in NVIDIA products since GeForce FX series. But that is really not that new as Inq showed it, DPM is not a new feature of RV670 and it was already used in the previous RV6xx...

You just messed the settings, there are 2 different fan control levels available in RT depending on hardware. You cannot use driver-level 2D/3D fan control on 8800 series by design, because fan is physically not connected to integrated PWM controller used by ForceWare to separate fan speeds in...

Small tip, which drastically simplifies navigation in RivaTuner: There are so called module activation launch items in "Launcher" tab, which allow you to create tray menu items for getting to any desired tab of GUI with a couple of mouse clicks. You can also create a shortcut for such item...

Placeholder for what? Give me at least one logical reason of using such pipe control scheme and leaving one unused (0-hardwired!) bit in the middle of pixel pipe control bitfield.

I've neither G71 nor G73 in my testrigs, I can only rely on Digit-Life/iXBT testers.

AFAIK, there is still 1 bit in control register -> 1 pipe mapping. It is very easy to check, new (beta) version of NVStrap driver is able to disable pipes on G71/G73 by masking the corresponding bits.

True if blocked pipes (if any) are faulty, false if they are hidden due to marketing issues.

Don't think so. Pixel pipe related bits of pipe config register are unified for whole NV4x family, each pixel pipe state is controlled by the corresponding bit, the difference between NV4x (e.g. between NV40 and NV47) is only the amount of bits in use (e.g. bits 0-5 for NV47, bits 0-4 for NV40...

Small update on that issue. I asked a tester with 7800 (I don't have it and able to analyze its' driver/BIOS only) and 3-domain clock monitoring capable beta of RT 15.7 to reproduce this situation. The assumption was correct, the driver does seem to use "min delta" clock generation rule...

They'll start on 11th. Today is the last boring day in the office. ;)

Also, I'm a bit sceptical about "new architecture" too. Currently I'm comparing NV47's clocking approach with NV40's one. As far as I can see now, the previous highe-end chip has that 3 independently clockable domains too, which are simply synchronically clocked with a single PLL. However, it is...

To be honest I'm a bit sceptical about "more than 3 clock domains". G70 BIOS's internals can be used as the simpliest way to verify amount of programmable clock domians in the core - there is a PLL programming routine, which _must_ switch all domains to bus clock during PLL programming (to avoid...

ALT, you shouldn't expect that "jumps" exactly at N*27MHz clocks. There can be different approaches for feedback divider selection, for example they can select closest divider generating a clock with smaller delta between target and the real one: e.g. when you set 440, abs(440-432) is less...

Small info update: According to report of testers using 15.7, the driver sets ROP clock to 418MHz in low power 3D mode (27 * 31 / 2). So hardware does seem to be able to generate more accurate clocks with no problems, at least in low power 3d mode, It is still unclean why such rough step is...

I hope that is is just the driver's limitation and there will be more flexible ROP frequency control in new drivers. The PLL they use for geometric domian is able to generate clock via: 2 feedback dividers, 2 reference dividers and 1 post divider. The PLL they use to clock ROP domain is...