Recent content by szatkus

Given that their GPU is 100mm2 smaller than 3080 it's a very good result.

I took a look at RDNA whitepaper and seems that everything is the same or larger, so there should be even more than 45MB of SRAM, but when I summed everything I found there it was a little over 14MB. I have no idea what else it could be.

I don't know how you came up with this. The largest cache on Navi 10 is L2 and it's just 4MB.

That's for sure will turn out great when one will wish 5700 for Christmas.

Duh, that's why I have B550 mobo next to me :)

That's right, but 5600 was an outlier. I don't think they ever cut down any GCN chip that much. Probably something related with yields on N7.

I would prefer something between, like 64CUs. Unless Big Navi would be cheap, then no problem, I can take that.

3080 has some ML features disabled, at least that's what I read on dev forums. For some people it's worth it.

Big companies usually produce a lot of patents, many of them are never implemented in anything.

Depends on the context. HBM is mainly used there is a need for, well, high bandwidth. There was of course that Intel-AMD processor and Navi 12 where HBM was in fact used to optimize power consumption, but those were premium products, where margins are high anyway.

Maybe Ryzen was postponed, but not Epyc?

Are there any Navi 10 die shot? HBM2 controller would be visible if it's the same chip and not Navi 12. Edit: oh, nevermind

After seeing 128-bit bus I didn't ever think it is. I wonder why they pushed this one into the driver before Big Navi.

I haven't even notice it. #define ASICREV_IS_VEGA10_M(r) ASICREV_IS(r, VEGA10) #define ASICREV_IS_VEGA10_P(r) ASICREV_IS(r, VEGA10) Vega 10 has never been released as a mobile part, right? There are some chips with V. I really can't find logic behind it, maybe Value, Mid and...

Yeah, that's my conclusion as well. I guess 20 was too much for Navi, so they've shrank it to shave off some transistors.