Recent content by metafor

IIRC, most x86 space processors do divide as part of their pipeline. I'm obviously not going to confirm anything but divides in ARM space is more of a separate iterative sequencer deal. Those take up a lot less space but it does mean divide throughput isn't very high, hence the desire for dual...

Also the Galaxy Nexus LTE. Tegra/Exynos still used SDIO for its modem communications; which made it unsuitable to work with the MDM9xxx series. I would imagine Exynos 5xxx resolves this. OMAP has never had this problem.

Divides are only available in scalar mode; there isn't a SIMD divide instruction. I'm not sure how permute would be handled with regards to forwarding to the arithmetic path. I realize that A15's SIMD/FP pipeline is far more integrated to the other pipes than it was in A9 but whether they're...

Actually, there are dual dividers in A15. I wouldn't expect it to be completely symmetrical, but the things I wouldn't expect to be symmetrical would be FP64 MUL and MAC. Perhaps VFP can't be dual-issued either. It could. And I agree public information doesn't say one or the other. But I'll...

Yes but you can interleave ADD/SH and other non-MUL instructions in there. I realize that's not as flexible or as preferable. The public information is the block diagram I've seen in various places: http://pc.watch.impress.co.jp/video/pcw/docs/513/347/p11.pdf For instance. There are...

Even the partial product tree isn't increased all that much for a base-16 multiplier. But more importantly, the actual tree can be mostly reused and shared by 4xINT32 without much waste. FP adds a lot of waste, but not in the partial product tree itself; the shifter for alignment is the biggest...

Integer multiplication doesn't cause quite that much extra area for doubling the width for a relatively sane implementation. Floating point, yes.

Depends on the MAC implementation. Chained implementations don't have much of a size advantage other than the bloat that comes with instruction tracking. How prevalent is a MAC type op in GPGPU applications compared to chains of MUL or ADD? Any matrix-based operations would obvious benefit...

I wasn't referring to fused vs unfused. I was referring to single MAC op vs standalone ops for MUL and ADD. Are there significant advantages to having a MAC op for most jighly parallel, loosely memory coupled algorithms?

What are the typical use cases for FP64 in GPGPU? Even Kepler takes a significant hit when performing MAC compared to standalone MUL and ADD, so I imagine MAC's aren't particularly desired?

The biggest problem (and often critical path) is alignment for FP64 MADD. Since a FP64 has a much wider range of exponents compared to FP32, the initial exponent comparator would have to be widen, the shift would have to be done over multiple cycles with the intermediates stored some place. The...

But if the FP64 datapath is separate and sufficiently low performance, nominal power consumption shouldn't be that much higher. Particularly when we're talking about a ~500MHz operating frequency.

Samsung does make discrete LTE modems. Albeit not true multi-mode like the qcom ones. Modem integration can cause quite a few hassles. Not the least of which is qualification and validation on top of heavier IP protection that requires encryption ROMs and thus, difficulty with chip bringup...

They started this SoC likely around the time ARM first announced the A7. I think you severely underestimate how long it takes to integrate something like that into an SoC; especially considering you're supporting a hybrid coherency model. I believe the Korean version of the Galaxy S3 has...

Krait's pipeline is significantly shorter than A15's though. I'm frankly very surprised they're only running at 1.7GHz. Perhaps it's a power consumption issue. A15's kinda power hungry.