Recent content by itaru

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    Nvidia Turing Product Reviews and Previews: (Super, TI, 2080, 2070, 2060, 1660, etc)

    maybe 2070
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    Nvidia Volta Speculation Thread

    https://translate.google.com/translate?sl=ja&tl=en&js=y&prev=_t&hl=ja&ie=UTF-8&u=http%3A%2F%2Fnews.mynavi.jp%2Farticles%2F2017%2F01%2F19%2Fnvidia_volta%2F&edit-text= While Xavier 's announcement is the first in Volta, Volta actually comes out as a product through science and technology "GV 100...
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    Nvidia Volta Speculation Thread

    volta has 128 bit core ? p.2-(c) 4-Wide SIMT lane detail http://research.nvidia.com/sites/default/files/publications/Gebhart_MICRO_2012.pdf gm104 has 5.2b transistors and 2048 core. Xavier has 512 core(128bit).
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    NVIDIA Tegra Architecture

    volta has 128 bit core ? p.2-(c) 4-Wide SIMT lane detail http://research.nvidia.com/sites/default/files/publications/Gebhart_MICRO_2012.pdf gm104 has 5.2b transistors and 2048 core. Xavier has 512 core(128bit). 512*4(128/32)=2048.
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    NVIDIA Tegra Architecture

    Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks http://www.rle.mit.edu/eems/wp-content/uploads/2016/02/eyeriss_isscc_2016_slides.pdf CVA is Eyeriss,maybe
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    NVIDIA Tegra Architecture

    Xavier has CVA(Computer Vision Accelerator). Maybe DL 20TOPs is spec of CVA. maybe CVA is like a Eyeriss.
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    NVIDIA Tegra Architecture

    https://www.computerbase.de/2016-08/nvidia-tegra-parker-denver-2-arm-pascal-16-nm/
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    NVIDIA Tegra Architecture

    http://www.nvidia.com/object/drive-px.html Scalable from 1 to 4 processors (2 next generation Tegra SoC and 2 Pascal GPUs) Dual NVIDIA Tegra® processors delivering a combined 2.5 Teraflops Dual NVIDIA Pascal discrete GPUs delivering over 5 TFLOPS and over 24 DL TOPS Interfaces for up to 12...
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    Tile-based Rasterization in Nvidia GPUs

    The tile check software that has been introduced I tried to compile.
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    NVIDIA Tegra Architecture

    64bit of PX2 will be a mistake. Probably it should be 8tflops in 32bit. 3840 cores are not 32bit; in the case of 16bit. Probably it is 1280 cores and 2560 cores in 16bit. Probably it is like that FP16 Tegra X2:2560 core(16bit),dGPU:1280 core(16bit) 2*(2560+1280)*2*1.56=23962Gflops FP32 Tegra...
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    NVIDIA Tegra Architecture

    http://emit.tech/EMiT2016/Ramirez-EMiT2016-Barcelona.pdf px2 2x Tegra X2 　4x ARM Cortex-A57 　2x NVIDIA Denver2 2x 3840-core Pascal GPU 　8 TFLOPS (64-bit FP) 　24 TFLOPS (16-bit FP) 1 GbE cluster interconnect
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    NVIDIA Tegra Architecture

    Drive px2 FP32:8Tflops FP16:24Tflops dGPU=a,Tegra P1=b(FP32 Tflops) 2*a+2*b=8 2*2a+2*4b=24 a,b=2 FP32 dGPU=2Tflops Tegra P1=2Tflops FP16 dGPU=4Tflops Tegra P1=8Tflops
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    Nvidia Pascal Speculation Thread

    https://forums.geforce.com/default/topic/929135/shield-tablet/nvidia-tegra-with-denver2-cpu-amp-integrated-pascal-gpu/
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    nVidia Denver discussion

    nexus9 android 5.1.1 update MTS shell@flounder:/ $ cat /proc/cpuinfo cat /proc/cpuinfo Processor : NVIDIA Denver 1.0 rev 0 (aarch64) processor : 0 processor : 1 Features : fp asimd aes pmull sha1 sha2 crc32 CPU implementer : 0x4e CPU architecture: AArch64 CPU variant : 0x0 CPU part : 0x000 CPU...
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    nVidia Denver discussion

    Thanks you. I also found a few things it seems. I think probably related dynamic code optimization. https://chromium-review.googlesource.com/#/c/210246/ https://chromium-review.googlesource.com/#/c/210247/ https://chromium-review.googlesource.com/#/c/210248/ rush: enable 128MiB MTS carveout...
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