Recent content by boipucci

You make a good point but it's two different sites using different testing methodology and tools that could alter results so maybe not be apples to apples, would be curious to see DF test on WDL A bit of both, i read here the benefits of moving i/o to same die and a quick duckgo search brought...

Considering the improvement from renoir IO being on the same die bringing it on par with desktop variant IPC despite having a quarter the cache (8MB vs 32MB) I'd say sharing sharing that cache between CCX will bring even further improvements. Also evidenced with Zen3 how this was one of the key...

You're missing the point... using my previous example thats 25mm2 worth of space in the 333mm2 estimate, that is space can be repurposed for PS5 I/O and other components

The way i understood Cerny talk is that the I/O block customizations are there to maximize streaming performance from SSD, the way he worded it even cache scrubbers are there to prevent stalls when streaming large amount of data from SSD. The only component left that could potentially amplify...

Yeah i use the term IC to refer to a cache system that will increase average bandwidth, given its numerous benefits im inclined to think it made it to PS5 in one form or another unless performance scales poorly with smaller pools I did and i repeat within that 333mm2 resides half of 6800 I/O...

You could well be right, i guess im not closing the posibility until we get undisputable proof Answer me this though (and this goes for you too @j^aws ): Let's say PS5 doesn't have IC why do you think they wouldn't invest an extra ~22mm2 for 32MB IC, perhaps too low a amount to make a difference...

True but some of those drops (33%) go beyond even the best case raw bandwidth gap (25%) if we assume xsx only uses 10GB total to make the most optimistic use of 560GB/s. Performance gap could be even bigger considering XSX is capped at 60. Having said that, its been confirmed those odd frame...

The first part of my comment was making the case to explain PS5 struggling more at ~4k coupled with rt to maintain <16ms frametimes as a result of cache misses from IC in specific scenes (however VGTech pointed out its a bug). BTW I don't think XSX has a "problem" with 120fps though i do have a...

You don't think their current cooling setup has enough wiggle room to handle an extra 40W? Besides I was referring to the scenario of MS going narrow and fast with some form of IC with a 36 to 44CU configuration. XSS doesn't use variable frequencies either... I think this would complicate their...

This is the part where knowing PS5's & 6800/6900 i/o size would help determine how much if any amount of IC will be possible Using 5700 i/o (~37mm) as baseline accounts for ~18mm2 that can be used for ps5 io after we halve navi21 Btw isn't L2 included with phy/mc in rdna? To use IC on a...

Continuing the Infinity Cache speculation... the latest DF face off (COD) results could perhaps be explained by IC? PS5 locks 60fps 95% of the time in 4k/RT mode (dynamic 2160p-1800p) and it chugs in specific set pieces momentarily dropping to 45fps/50fps for a couple of seconds while the XSX...

People are absolutely welcome to do that, i already saw a pretty good analysis from @j^aws on ree next gen thread using XSX as a baseline. Different perspectives are always helpful to find answers It just occurred to me the other day to use navi21 as a baseline when i saw its die size which i...

I assume is the same chip and same bus sans ic As anything the proof is in the pudding, you can see it allowing to trade blows with nv cards that sport wider memory buses and faster gddr6x chips

I think Navi21 layout is more comparable to PS5 especially if we are discussing IC, MS clearly took a slightly different route That's accounted in the 4 extra PHY I added later (30mm2) Front end scales with SEs no? I assume 4SEs need a beefier front end than 2 Yes im keeping an eye that, this...

PS5 is Navi21 design halved, same SA/SE layout and same high frequency pipeline. RDNA2 it's optimized for high frequencies getting the most utilization of hardware. In the slides is empathized in each part of the pipeline. So far we know XSX SA/SE layout goes beyond 10/20 seen in Navi21, there's...