RDNA4

[Seanspeed]

Maybe they didn't have enough time to prepare it. I'd also expect the chiplet part would be 3nm. 400mm² 3nm monolithic die could be quite expensive, while 400mm² 4nm monolithic die would have quite a high power consumption (lowering clocks would hurt performance = lower margins). I believe they found a better way how to utilize the available manufacturing capacities, so the used them that way.

Well the hope is that RDNA4 fixes a lot of the inefficiencies of RDNA3, so you could do performative clockspeeds at 4nm with semi-reasonable power draw. RTX4080 is a ~400mm² GPU on 4nm, and while it's rated at 320w, that could easily be lowered to ~250w without hurting its general competitiveness much. But that might have helped clue people in that AD103 wasn't actually a high end part....

Either way, if AMD wants to do anything meaningful here, they're gonna need to stop being so margin-obsessed. Pushing out clocks to scrounge an extra 3-5% performance to get it closer to some higher tier Nvidia competitor so they can charge as much as possible will just mean lackluster reviews and lower sales.

 

[trinibwoy]

Well the hope is that RDNA4 fixes a lot of the inefficiencies of RDNA3,

Right. If you can deliver mainstream performance and power in ~240mm^2 you should be able to hit high end performance and power by scaling up.

 

[Granath]

Chiplet-based GPUs would need CoWoS packaging. CoWoS capacities are limited, so it makes sense to use all the reserved capacities to manufacture high-margin products ($x0 000 accelerators) instead of low-margin ($x00) gaming GPUs.

RDNA3 is not a COWOS.

 

[trinibwoy]

RDNA3 is not a COWOS.

It’s also not a “real” chiplet arch

 

[Kaotik]

It’s also not a “real” chiplet arch

Huh? Since when is "real chiplets" dictated by shader engines split between chiplets?

 

[trinibwoy]

Huh? Since when is "real chiplets" dictated by shader engines split between chiplets?

I was being facetious. Bandwidth requirements and hence interconnect complexity is on a different level to RDNA 3 hence the need for CoWoS.

 

[entity279]

Sure but it doesn’t explain why AMD didn’t go for a ~400mm^2 RDNA 4.

They didn't design a big single shader die in time, as they were planning to go chiplets for high end. Scrapping high end later in the cycle, it was already guaranteed the big die would be ready later than the rest. They probably also lack the manpower needed to allocate for this unexpected project.

This is the most likely explanation to me

 

[trinibwoy]

They didn't design a big single shader die in time, as they were planning to go chiplets for high end. Scrapping high end later in the cycle, it was already guaranteed the big die would be ready later than the rest. They probably also lack the manpower needed to allocate for this unexpected project.

This is the most likely explanation to me

Maybe. N48 was also a last minute pivot right? If they could do that they could have potentially aimed for something bigger for plan B.

 

[yuri]

We can't rule out even a great reshaping of the long term goals of RTG. Seeing the characteristics of RDNA3-based products launched 2+ years after RDNA2 screams for reevaluation.

Btw RDNA3 family consists of only 3 chips + 1 APU, compared to RDNA2's 4 chips + 3(?) APUs. This means there were not that many designs to make this gen.

 

[Kaotik]

We can't rule out even a great reshaping of the long term goals of RTG. Seeing the characteristics of RDNA3-based products launched 2+ years after RDNA2 screams for reevaluation.

Btw RDNA3 family consists of only 3 chips + 1 APU, compared to RDNA2's 4 chips + 3(?) APUs. This means there were not that many designs to make this gen.

2 APUs, Phoenix and Phoenix2 are different chips. Also should RDNA "3.5" be counted as separate? That's coming to at least 3 APUs by the looks of it (Strix Point, smaller version of Strix Point and Strix Halo)

 

[no-X]

+ possibly Sonoma Valley