Xenos Chip Package

Discussion in 'Beyond3D News' started by Dave Baumann, Jun 16, 2005.

  1. Jawed

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    The NV40 pixel pipeline is way complicated:

    http://www.3dcenter.org/artikel/nv40_pipeline/index_e.php

    The article describes a few limitations in the pipeline architecture of NV40 that could be removed in G70 (e.g. special functions are distributed asymmetrically across the two ALUs and register read bandwidth is limited to 4x 32-bit reads), so we really have to wait and see.

    Jawed
     
  2. pjbliverpool

    pjbliverpool B3D Scallywag
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    Guess...
    Im Pretty sure the shader figures are only half of that. i.e 48 Vec4 and 48 Scalar per cycle with texture ops.

    That compares to the NV40 which is capable of 32 Vec3 and 32 Scalar per cycle without texture ops. (in the pixel shaders alone)
     
  3. The GameMaster

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    ATI stated that each pipeline can process TWO shader operations per cycle, and if programmed for correctly... double that. TWO shader operations (if I am not mistaking each shader operation requires 4 ALU operations or basically a Vec4 operation) basically means 96mad4 operations per cycle for all 48 pipelines AND 96scalar operations per cycle (Basically 48 billion shader operations per second at 500mhz). If you do mad4 operations instead of scalar operations then that 96mad4 becomes 192mad4 operations per cycle (4 shader operations per pipeline or 96 billion shader operations per second) if what ATI claimed is true. Due to the fact I promised another person on another forum that I would discontinue comparing GPUs until the NV50 GPUs are launched this week I am going to stop short of continuing this point for now. This is a particullarly interesting subject that I will be looking at pretty closely in the future. Have a good night!
     
  4. nAo

    nAo Nutella Nutellae
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    WHy we should double that? each Xenos's ALU can do 2 shader ops per clock.
    That's wrong. Shader ops are not a 'fixed' concept, regarding Xenos ALUs a first shader ops is a vec4 operations, the second shader op is a scalar operation. We already stated this many many times on this board, maybe you should at least read last threads about Xenos.

    No. What ATI stated it's true, what you're writing here it's not.
    On Xenos you can do 48 mad4 operation per cycle, nothing more than that.
    For the tenth time..ATI stated a Xenos's ALU can do 2 shader ops per clock, a vector4 op and a scalar op.

    Great promise, keep it.
     
  5. Nemesis77

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    Oooh, shiny!
     
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