Xenos Chip Package

Discussion in 'Beyond3D News' started by Dave Baumann, Jun 16, 2005.

  1. Dave Baumann

    Dave Baumann Gamerscore Wh...
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    As our "<a href="http://www.beyond3d.com/articles/xenos/">ATI Xenos: XBOX 360 Graphics Demystified</a>" article investigates, the graphics processor for the XBOX 360 console is split into two elements, the main parent "shader core" (manufactured by TSMC at 90nm) which handles most of the graphics operations and the ALU arrays for processing shader programs and a secondary, daughter die (manufactured by NEC at 90nm) which handles the all the sample operations (colour read/blend/write, Multi-Sample AA, Z operations, etc.) and a fast dedicated 10MB of eDRAM that acts as the processors primary frame buffer, that has 256GB/s of bandwidth available to it. We've been supplied with an image of the chip package for the Xenos graphics processor:
    <p align="center"><i><font size="1">Click Image to Enlarge</font></i>
    <a href="http://www.beyond3d.com/news/images/image.php?img=http://www.beyond3d.com/articles/xenos/images/c1.jpg&comment=ATI Xenos" target="new"><img border="1" src="http://www.beyond3d.com/articles/xenos/images/c1s.jpg"></a>
    <i><b><font size="1">ATI Xenos Graphics Processor</font></b></i></p>The parent/daughter die is quite clearly evident on the same package from this image. While the 232M transistor figure for the parent was given to us by ATI we are still trying to establish a more official figure for the daughter (even though these things are very much estimates). We've speculated that the 150M figure that appeared when XBOX 360 was first announced may just relate to daughter die, however another figure that has arisen is 100M - judging from the die sizes the daughter die doesn’t have more than half the area of the parent, which would give indications towards the 100M side although 80M of those transistors are DRAM which may be more dense than the logic circuitry that will dominate the parent die.

    <i><b>Update</b>: ATI have clarified the daughter, eDRAM/sample logic die count to be 105M transistors.</i>
     
  2. Acert93

    Acert93 Artist formerly known as Acert93
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    Cool Dave, thanks for the update. For some reason I did not imagine the eDRAM die as being totally external.

    Btw, they let you write up about it, they gave you a picture... any chance they will let you benchmark it :D
     
  3. Shifty Geezer

    Shifty Geezer uber-Troll!
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    How do they assemble these? Fab the package + GPU core, then add the daughter die? Fab daughter die and GPU silicon separately and assemble the two parts onto the package? I'd have though this a reasonably costly processor, compared to a single chip structure from a single manufacturer. Any ideas of cost issues for the launch silicon?
     
  4. blakjedi

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    Was thinking the same thing... Dave you da Man!
     
  5. pc999

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    Anyone know the size(bits) of the bus betwen the parent and the doughter die?
     
  6. tEd

    tEd Casual Member
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    128bit
     
  7. Dave Baumann

    Dave Baumann Gamerscore Wh...
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    Nope.
     
  8. TheAlSpark

    TheAlSpark Moderator
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    a couple thousand? :)
     
  9. tEd

    tEd Casual Member
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    256bit
    512bit
    1024bit

    choose one

    I thought you mentioned it's running with 2Ghz. Must have imagined it. If the bus runs with 500hz as the chip then 512bit
     
  10. nAo

    nAo Nutella Nutellae
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    It can't be a very wide bus..it's still external.
     
  11. Dave Baumann

    Dave Baumann Gamerscore Wh...
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    tEd, you're going the wrong direction.
     
  12. tEd

    tEd Casual Member
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    As usual :lol:

    So it's &lt;128bit. SDR or DDR bus?

    64bit @ 2ghz ddr
     
  13. soylent

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    Is breaking it up into 2 dies due to considerations of yield, because NEC can't manufacture the parent die which is on a different process, because microsoft may want to be able to migrate the parent/daughter die to a smaller process independently of each other or what exactly?

    If the daughter die was just EDRAM and nothing more it would be obvious why the split was like this, well I'd assume NEC wasn't capable or didn't want to bother making more than just the EDRAM anyway...
     
  14. Rockster

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    I think you finally got it tEd.
     
  15. ralexand

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    I thought the article said 32-bit connection between parent and daughter? Why is it a daughter card and not a son? :D
     
  16. Jawed

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    Why is it motherboard and not fatherboard?...

    Jawed
     
  17. JoshMST

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    Yes, splitting the two cores up is a pretty good idea. Getting edram to work is not a simple task, which is why they are using NEC's process. Who remember's the Glaze 3D with the edram? Chips were produced, but they had to utilize Infineon's process as it was the only consumer level process that would allow the use of edram.

    So, NEC fabs the daughterchip, TSMC the main chip, and somewhere in Korea/Indonesia they take the two bare die and put them on a substrate package and test it out. NVIDIA does much the same thing (though not as complex) with their NV45 (NV40 chip with HSI on the same package).
     
  18. bluefox

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    .

    Anyone notice the GPU-DBG designation on the chip.

    Is it possible this is a "debug version" and not the GPU we'll find in retail boxes ???

    .
     
  19. nutball

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    Pins &amp; sockets, pointy things and holes. *cough*
     
  20. Titanio

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    It's undoubtedly a "beta" version at least, the one that's going into beta dev kits that are shipping now, probably. I think I read that mass production of the final GPU wouldn't begin till July or August.
     
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