XBox2 specs (including graphics part) on Xbit

Load balanced shaders. 8)

 

Ahhh, hadn't noticed your post when I posted the link on the console forum, where a discussion had sprouted thanks to another story about an early Xbox2 launch: http://www.beyond3d.com/forum/viewtopic.php?p=267146#267146

 

wow anyone notice that the three processors are all on the same die !!!! ibm has been doing this sort of stuff on there mainframe cpu's for years wow ... i just saw one with 9 processors and 32 meg cache ....it was amazing !!!


retsam

 

Sounds like it relates (IIRC) to a lot of what Huddy was saying in his "save the nanoseconds" presentation he gave at GDC.

The chip would have "generic shader pipelines", and balance between what we'd call "vertex" shading and "pixel/fragment" shading at any given moment.

That being said, there would be an additional, and "separate" pipeline...the "geometry processor" (or something like that)...which does all the tesselation / deforming of the geometry, before it hits the shaders...

 

Considering that MSFT is pushing hard for a mid-2005 launch ( http://www.gamesindustry.biz/content_page.php?section_name=pub&aid=3348 ), would this GPU not *have* be based on R500 tech?

 

I would save that thought...

 

For when?

 

Grrr....

 

Dam why do you always do that?!

IIRC you suggested once that the R500 was too be lunched a lot earlier then you had originally thought... like towards the end of the year. Maybe MS is on schedule for an early xbox 2 launch? Or possibly that ATi will launch the GPU in advance of the xbox 2 in a similar manner that nvidia launched the nv20 architecture which the original xbox was based on? Bah I know I won't get anything out of you on that... so why the hell am I bothering?? :?

 

Based on the specs, would the GPU be considered 8x2 in a "traditional" sense? (Based on dual quad spec, plus 16 bilinear texture fetches per cycle.)

It's also not clear to me how many z/stencil reads per cycle it's capable of..

 

I believe this is the chip that is supposed to throw traditional pipes out the window, I think that's the "load balancing" bit.

 

Well, load balancing AFAIK pertains to shader throughput. Not pixel writing and texture reading ability. There still has to be upper limits on that, separate from pixel/vertex shader specs.

 

Only 2 quads per cycle (8 pixels) ?
48 ALU ops which means 6 ops per pipe per cycle, taking co issuing in account we are looking at 3 shader units per pipe ?

16PS inputs interpolate : great !

 

2x

 

Seems reasonable for a console...considering its 500 Mhz, and we're still talking TV resolutions...not 1600x1200 PC resolutions.

It will be interesting to know if ATI would classify this as an "8 pipe architecture" or an "24 pipe" (number of shader units) architecture.

I'll take your word for it.

 

2x what?

 

Well it states the EDRam block is capable of 4 Quad Z+stencil writes (512bit write port) and 2 quad z+stencil reads (256 bit read port).

 

Ahh....missed the EDRam block...

 

Um, you were on a roll untill here. Hopefully, note I said hopefully, the console vendors will make it adventageous to move beyond the DTV resolutions of 480i or 480p. There has been talk of 720p and 1080p, take that as you will.