Xbox 360 Shortage Caused By Low Xenon Yields...Is Cell Affected?

[Alpha_Spartan]

Microsoft says Xbox 360 shortages are strictly down to a shortage of chips. The company says the shortage is such that a decision to delay launch was seriously considered.

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Does this mean that Cell yields should be better, worse or about the same? Discuss.

 

[Synergy34]

I doubt it effects it that much, maybe just on the IBM side of production and how much can that really be at this point? Sony and Toshiba have to be able to produce the bulk of them I would think.

 

[avaya]

I doubt it effects it that much, maybe just on the IBM side of production and how much can that really be at this point? Sony and Toshiba have to be able to produce the bulk of them I would think.

Initial PS3 Cells will all be fabbed by IBM.

 

[Alpha_Spartan]

Cell is a larger chip isn't it?

 

[Shifty Geezer]

The article doesn't say which chip or chips are the bottleneck. Could be XeCPU, Xenos main die, or maybe Xenos+eDRAM complications. As the fabs for Sony's components are different to MS's components, their aren't any obvious parallels, save that big complicated chips don't get good yields

 

[Jov]

I wonder if this will effect Australia when it launch in March?

 

[arjan de lumens]

While CELL is rather large, the fact that it is set up to have a redundant SPE should help its yield substantially.

 

[drpepper]

Hey! that's my newspaper. I'll have to pick one up to read the related article...

This doesn't bode well for Cell IMO but then again it's not released yet so I guess it's a wait and see.

While CELL is rather large, the fact that it is set up to have a redundant SPE should help its yield substantially.

The problem with the Cell is that it has to have at least 7 working SPEs and the PPE. I don't know the statistics around chip fabbing but the probability of 8 cores out of 9 passing is lower than a 3 core chip. But like Shifty said, they did not mention specifically what was in low yields.

 

[expletive]

"We're getting a little less, but not much less than the yields we expected, and we know that the yields we expected will probably outrun supply."

DOesnt sound like a huge problem, but just enough to put htem behind the supply curve. The article itself is a little too "gloom and doom" if all they are going by is the quote above.

 

[Dr. Nick]

Well some devs already had dev kits with Cells in them before E3 while the first machines with Xenons didn't show up until August. We didn't really see any demonstrations of the Xenon before the beta kits.

IBM, Sony, and Toshiba are probably on track with the Cell and all 3 companies can manufacture the chips. It also seems like IBM has more riding on the Cell than they do with the Xenon. I think when the PS3 launches the Cell will have better yields compared to what’s going on with the Xenon right now.

Also the Xenos could play a part in the low yields as well

 

[Shifty Geezer]

The title has changed to 'Low Xenon Yields' but I'm still not seeing where specifically the CPU was identified as the bottleneck. The article says

In these new consumer electronics devices based on new chips, there's always the question of what yield will you get out of the manufacturing process of the new chip. We're getting a little less, but not much less than the yields we expected, and we know that the yields we expected will probably outrun supply.

Where's the info that it's the CPU coming from?

 

[avaya]

The problem with the Cell is that it has to have at least 7 working SPEs and the PPE. I don't know the statistics around chip fabbing but the probability of 8 cores out of 9 passing is lower than a 3 core chip. But like Shifty said, they did not mention specifically what was in low yields.

That’s based on the flawed assumption that an SPE and a PPE have the same die area.

The SPE redundancy in Cell should help it considerably but it maybe starting from a relatively weaker position to begin with anyway.

 

[wireframe]

The problem with the Cell is that it has to have at least 7 working SPEs and the PPE. I don't know the statistics around chip fabbing but the probability of 8 cores out of 9 passing is lower than a 3 core chip. But like Shifty said, they did not mention specifically what was in low yields.

No. If there is a single defect (that is not masked) in one of the three Xenon cores then the entire chip is defective (or core where the error occurs, if you will). In Cell you can have that one defect and you're lucky if it's in one SPE; then you just disable that SPE. You are thinking backwards. The more independent and non-crucial components you have in a chip the less likely you are to have a total loss.

In the case of Cell you have 8 SPEs and 7 need to be working. If the PPE is defective the whole unit goes. Think errors over an area. The SPEs cover roughly two thirds of the die. Let's forget redundancy and assume any error will be a complete loss in that unit of the CPU.

If you have a single error in the PPE you lose
If you have a single error in the L2 cache you lose
If you have a single error in the EIB you lose
If you have a single error in the memory interface or FlexIO you lose
If you have a single error in the SPE region you win (because you disable the affected SPE)

With Xenon you lose all the time. You don't have a redundant core to disable.

The amount of redundancy increases the probability of a functional chip. In the case of the Cell you have an entirely redundant SPE. The fact that the SPEs cover a significant area increases the probability that an error will be located in an SPE.

 

[arjan de lumens]

If you have a single error in the L2 cache you lose
If you have a single error in the EIB you lose
If you have a single error in the memory interfeace or FlexIO you lose

If you use ECC (or redundant rows/columns in case of the L2 cache), then a single error in either of these components isn't going to break you chip. It's rare these days to see chips with large on-chip buses or memory blocks that aren't protected this way.

 

[Alpha_Spartan]

The article doesn't say which chip or chips are the bottleneck. Could be XeCPU, Xenos main die, or maybe Xenos+eDRAM complications. As the fabs for Sony's components are different to MS's components, their aren't any obvious parallels, save that big complicated chips don't get good yields

Didn't we find out a few months ago that Xenos yields were excellent. So much so that people were wondering if MS could bump up the clock speed.

 

[drpepper]

So what you're saying is that the most likely error to occur is related to the area covered by the SPEs?

The way I'm thinking is, if there's an error on 1 SPE, fine, it's disabled. But what if there's an error on another spe of the same die, cause then it's rejected for the ps3? Basically I'm thinking of it in terms of probability. Probably the wrong way to go but it's a form of thinking I'm used to being a chemistry background. ie, the probability of an SPE failing is independent of the success rates of the other SPEs on the same die.

I just want to get this cleared, so you're saying there's a more likely chance that 1 error will be on the SPE and not the other non-redundant areas of the chip? But this of course is assuming that you only get 1 error per chip. And when I mean error I mean a flaw that makes the circuit unusable.

 

[wireframe]

If you use ECC (or redundant rows/columns in case of the L2 cache), then a single error in either of these components isn't going to break you chip. It's rare these days to see chips with large on-chip buses or memory blocks that aren't protected this way.

That's why I said without redundancy. There is no reason to count with redundancy here because we must assume both chips have some level of redundancy/masking. If we strip this component we see that the Cell has an advantage due to structure and implementation.

 

[avaya]

I just want to get this cleared, so you're saying there's a more likely chance that 1 error will be on the SPE and not the other non-redundant areas of the chip? But this of course is assuming that you only get 1 error per chip. And when I mean error I mean a flaw that makes the circuit unusable.

Exactly.

 

[Joe DeFuria]

I just want to get this cleared, so you're saying there's a more likely chance that 1 error will be on the SPE and not the other non-redundant areas of the chip?

No, he's saying that there is SOME chance that 1 error will be on the SPE, vs. Zero chance of on error being on a "redudundant unit" of Xenos, because it doesn't have any.

(I say "redundant unit" in quotes, because both Cell and Xenos are going to have certain other types of redundancy, as others are explaining.)

 

[Joe DeFuria]

In the end, it's really difficult to say anything about how "slightly less than expected" yields for Xenos relates to Cell yields.

To even begin any discussion at all, we'd have to know relative chip sizes...and then we'd have to make some complete guesses / assumptions as to typical error rate per wafer for both architectures...pretty fruitless.

We can assume for example that Cell is larger than Xenos, which would mean that "all else being equal", there will be on average more defects per die. First of all...all else won't be equal...but if we assume that, we'd have to know die size to guess on whether or not the redundant SPE would improve yields to compensate for increased die size.