I am not convinced that it is even theoretically possible to implement affinity, at least to the levels described in some of the research papers from the IBM side.
Imagine, if you will, that I want to have three adjacent SPEs running a pipeline between XDR and BIO, and I don't want traffic from XDR to them, or from them to BIO, to compete with the CPU's access to EIB. So, using the 0-3 top, 4-7 bottom labeling, I need three of the 4-7 SPEs.
That may not be possible if the reserved SPE and the defective/disabled one are both on that side of the chip.
So there's cases you can describe where a given layout would be advantageous, but would be possible on some PS3 systems and not others. So you have to go without.
I don't know how much of a difference affinity makes in the real world; the IBM research papers I saw suggested it was noticable but not huge.
Imagine, if you will, that I want to have three adjacent SPEs running a pipeline between XDR and BIO, and I don't want traffic from XDR to them, or from them to BIO, to compete with the CPU's access to EIB. So, using the 0-3 top, 4-7 bottom labeling, I need three of the 4-7 SPEs.
That may not be possible if the reserved SPE and the defective/disabled one are both on that side of the chip.
So there's cases you can describe where a given layout would be advantageous, but would be possible on some PS3 systems and not others. So you have to go without.
I don't know how much of a difference affinity makes in the real world; the IBM research papers I saw suggested it was noticable but not huge.