Updated Cell roadmap

Discussion in 'CellPerformance@B3D' started by liolio, Jun 26, 2008.

  1. liolio

    liolio Aquoiboniste
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    #1 liolio, Jun 26, 2008
    Last edited by a moderator: Jun 27, 2008
  2. catisfit

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    It's labelled as concept, but it makes sense.

    SW compatibility between current and next-gen Cell
    100% backward compatible
    Performance on PPE significantly better
    Performance per SPE equal or better
    – Significantly better on applications that benefit from new instructions
    Better inter-SPE latency
    More on-chip memory
    Better main memory latency and bandwidth

    Nice slide breaking down Folding@Home performance too.
     
  3. one

    one Unruly Member
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    Cool find!

    Note: Traditional Codes run the PPU & NG PPU’ (C1 core)

    IBM PowerXCell 32iv (4PPE’+32 eSPE)
    ~3.8 GHz
    1 TFlop (est.)
     
  4. Entropy

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    Page 11 has the interesting, or rather tantalizing info.
    The PPE has been beefed up, communication between units has improved further, new SPE instructions, and perhaps most intriguing, better main memory latency and bandwidth. I really wonder what their new memory subsystem looks like, this could be just what the doctor ordered for a lot of scientific computation. The 2010-2011 timeframe however hints at PS4 deployment - if scientific computation had been the main target, the slide indicates that 45nm manufacturing is available a year and a half earlier. Perhaps the "concept" design depends on Sony committing to using it.
     
  5. Carl B

    Carl B Friends call me xbd
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    Pages 16 and 17 speak to several of the practical strengths of the architecture.

    For pages 11 and 12, I'm not sure it's clear whether the 32iv is part of the next-gen Cell or not, or whether it's just an extension of the 8i. Or whether those two ideas are even functionally different...

    I read page 11 to be the arc of the current architecture though, with page 12 speaking to future, more fundamental changes. Changes I would expect for us to see beginning at 32nm and the development of the PS4. Good find by the way though liolio; nice to see IBM lay out the industries and business segments they're looking to expand Cell into.
     
  6. patsu

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    The forward looking slides read like a wish list though. Nothing concrete/measurable yet except for the target number of cores, clock speed and estimated FLOPs.

    I think many people are looking forward to:
    * A more powerful PPU
    * Larger Local Store
    * Faster interconnect

    I really like the slides, especially the "Solution Examples". They are real and yet exciting. ;-)
     
  7. Carl B

    Carl B Friends call me xbd
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    I don't know if the "more on chip memory" refers to the local storage though; I'd think L2 cache in general to complement the more robust PPE. I spoke with one of the Cell team members last year and at least at the time they didn't feel the need for local store enlargement due to the negative effects it might have on latency. Not that views may not have changed on the matter since then...

    For the moment I'm separating out the 32vi as a progression of the current Cell, and the 'forward looking' slide to some future chips not indicated on the roadmap.
     
  8. one

    one Unruly Member
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    As for PowerXCell 32iv it should be compared with the one on the older roadmap.
    http://www.lanl.gov/orgs/hpc/roadru...unner System Overview Oct 17, 2007 (LAUR).pdf
    (See page 10)

    The older version was

    Next Gen
    (2PPE’+32SPE’)
    45nm SOI
    ~1 TF-SP (est.)

    in 2010. But PowerXCell 32iv is almost 2011. My guess is they are planning 32nm for it. Since Roadrunner proved its concept, the next logical step for IBM as a vendor is to cut the cost by removing Opteron nodes while increasing PPE for control jobs unless x86 compatibility is crucial.

    It's now clear that PowerXCell 32iv has eSPE, DP-enhanced SPE. As games won't need DP, I think the 2PPE’+32SPE’ next-gen Cell with features in the page 11 at 45nm SOI is a good candidate for the PS4/PS3.5 CPU in the main trunk of the Cell/B.E roadmap.
     
  9. Lucid_Dreamer

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    I think manufacturing an extra Cell chip with a different configuration would not allow them to push the cost down (through volume) like they are doing with the current Cell. Therefore, I believe they might go with the 4 PPE 32 SPE config. for both uses.
     
  10. Crossbar

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    Thanks for the link.

    No mentioning of IBMs SOI EDRAM though.

    32MB of 3:rd level cache would offload the memory IO quite a bit.

    Edit: Found this new article on the EDRAM topic.

     
    #10 Crossbar, Jun 29, 2008
    Last edited by a moderator: Jun 29, 2008
  11. handglobe

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    The link doesn't work for me. By chance did anyone save a copy of the pdf?
     
  12. rpg.314

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    I wish to go through the new roadmap in the first post, does any body have it by any chance? The link is not working for me.
     
  13. Carl B

    Carl B Friends call me xbd
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    Hey Rpg.314 (and handglobe), sorry guys but the .pdf seems lost to the void of the Internet. You don't really need the picture though to tell you the truth - the discussion we had concerning it highlights all the key points one could have gleaned from it. I would have saved it myself if I thought it would disappear, but it is what it is.
     
  14. silhouette

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    Btw, 4-PPE+32 SPE chip would be backwards compatible with 360 CPU too (given that it includes the enhancements done to current PPE).
     
  15. Carl B

    Carl B Friends call me xbd
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    The XeCPU includes instruction support not present on the Cell PPE, inclusive to everyone's knowledge of the 32-SPE Cell discussed here.
     
  16. catisfit

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    Here it is (I have the PDF):

    P10:
    [​IMG]

    P11:
    [​IMG]

    P16:
    [​IMG]

    P17:
    [​IMG]

    P22:
    [​IMG]

    I don't think any other pages were mentioned in the discussion above.
     
    #16 catisfit, Jul 31, 2008
    Last edited by a moderator: Jul 31, 2008
  17. Carl B

    Carl B Friends call me xbd
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    Thanks Catisfit, I'm sure a lot of folk that missed these the first time around will appreciate your effort here.
     
  18. rpg.314

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    Yes, and I am one of them.
     

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