Umh..weird patent

[nAo]

I've just found a patent issued by nvidia's CEO and other nvidia guys:
System and method for accelerating a special purpose processor

Embodiments of the invention accelerate at least one special purpose processor, such as a GPU, or a driver managing a special purpose processor, by using at least one co-processor. Advantageously, embodiments of the invention are fault-tolerant in that the at least one GPU or other special purpose processor is able to execute all computations, although perhaps at a lower level of performance, if the at least one co-processor is rendered inoperable. The co-processor may also be used selectively, based on performance considerations.

now..I can't understand what they're trying to patent here.
Is it some weird GPU functional redundancy?

 

[Geo]

Keerist! Looks to me like they are trying to patent multi-gpu/sli/crossfire/mvp [take your pick].

Edit: I still think it could be read that way (particularly keeping in mind that whole "special purpose processor" is explicitly defined to include a GPU). Or possibly trying to patent the interaction of a driver with an sli setup, which would have the same result if granted.

Could also be (either instead or in addition) keeping an SLI going if one of the GPU's fails.

Tho this was kind of interesting:

11. The system of claim 10, wherein the transformed data includes a first pass z-cull information and the result includes a second pass z-cull information.

What's up with that?

And this:

20. A method for processing graphics data, comprising: creating vertex buffer data in a driver; transforming the vertex buffer data to produce transformed vertex buffer data, said transforming including at least one of culling and shading a plurality of vertices in the vertex buffer data using a co-processor; receiving the transformed vertex buffer data in a special purpose processor; and rendering the vertex buffer data using the transformed vertex buffer data, the rendering performed in the special purpose processor, said rendering performed more quickly than if the special purpose processor had received the vertex buffer data and not the transformed vertex buffer data.

And this looks an *awful* lot like patenting sli application profiling:

21. A method for selectively using a co-processor, comprising: determining whether use of a co-processor would improve performance; processing an input in a special purpose processor if it is determined that use of the co-processor would not improve performance; and processing a transformed input in the special purpose processor if it is determined that use of the co-processor would improve performance, the transformed input being a result of processing of the input by the co-processor.

23. The method of claim 21, wherein determining is based on a predetermined list of applications where performance is improved through use of the co-processor.

 

[KimB]

Might be a method of load-balancing between the RSX and Cell, but that seems pretty unlikely.

 

[ERP]

Looks like general load balancing.

Use a CPU or other coprocessor to transform the verts if it's faster to do so.....

I hope the patent is more specific thatn what's beeen posted here.

 

[Demirug]

Think about an IGP that supports the GPU as Coprozessor.

 

[Guden Oden]

Could the "coprocessor" the patent talks about (as opposed to the "special purpose processor", aka GPU) be some kind of motherboard-mounted new and unknown Nvidia ASIC, perhaps something that runs the (majority of) the graphics driver to reduce CPU load?

It does say coprocessor after all, so that really can't mean the CPU...

 

[nAo]

Think about an IGP that supports the GPU as Coprozessor.

SLI between a IGP and a GPU?

 

[Demirug]

Think about an IGP that supports the GPU as Coprozessor.

SLI between a IGP and a GPU?

Not that kind of SLI we already know. AFR works bad if the two units don't have the same speed. SFR can work but in the case of a IGP and a GPU it is possible that there are differences in featureset and options.

In the case of a IGP+GPU setup you need to think a little bit different. But the patent already show us some examples.

Let's take DOOM III. The first thing it done every frame is to render everything to the Z-Buffer. This is need for the stencilshadows. If we have an IGP we can assign this Z-Pass to it. The GPU still renders the shadow and light passes from frame n but the IGP works on the Z-pass for frame n+1. After the GPU is done with frame n it will take the new z-buffer that is already done by the IGP.

There are many other possible ways how the IGP can help the GPU. Render the shadowbuffers, doing some vertexprocessing, tonemapping and postfilters, ...

If they use some kind of TurboCache it sould be easy for both chips to share memory.

 

[_xxx_]

There are many other possible ways how the IGP can help the GPU. Render the shadowbuffers, doing some vertexprocessing, tonemapping and postfilters, ...

Maybe it's a PPU from nV?


// runs...

 

[Demirug]

There are many other possible ways how the IGP can help the GPU. Render the shadowbuffers, doing some vertexprocessing, tonemapping and postfilters, ...

Maybe it's a PPU from nV?


// runs...

If you take a look at the patent I am linked there http://www.beyond3d.com/forum/viewtopic.php?t=23415 you will see that a PPU and this nVidia patent are very different.

 

[_xxx_]

It was of course just a joke

 

[Geo]

I'm beginning to wonder if this patent provides a link (however twisted and not-quite-right) to the persistent "dual core" rumors we've been hearing about NV.

 

[pc999]

Would Xenus be like this?A co-processor with the GPU?

 

[darkblu]

though i read only the here-quoted excerpts i agree with chalnoth and ERP - seems like an apparatus for load ballancing. looks like a performance estimate is involved too.

 

[Geo]

I dunno. Seems to be a lot of focus on vertex's and z operations, in that they are specifically mentioned at a few spots. Yet at the same time, it makes a point of these ops still being able to be done on the GPU if the co-processor isn't available or if it is determined it wouldn't help.

Could they be after trying to alleviate some of the bandwith constraints of not being able to get past 256-bit because of die size by offloading intensive vertex and z-ops to another chip with its own bus, that only has to pass results (and thus saves bandwith) to the GPU? You'd still have to have some of this on the GPU as well, so you can downscale down the product range (just sell the GPU without the co-processor), but maybe you only put 2 VS in your GPU and another 6 (or 8 or whatever) in the coprocessor? We've seen ATI (not as sure about NV) take some Z optimizations out down the product range, for instance. . .

 

[Xmas]

The patent specifically mentions the possibility of the "co-processor" being part of the core logic, e.g. being an IGP. And I think this is the main intention of the patent.

 

[Geo]

Hmm. Well, that would give them a platform advantage over CrossFire presumably.

 

[j^aws]

Seems like a WGF 2.0/ unified shader patent to me because of the load-balancing. Where as ATI's Xenos would load-balance at the hardware level, this patent suggests it's at the driver level.

Instead of identical execution units like Xenos, the load-balancing seems to be between optimsed units and non-optimised units relative to the task. E.g,

CELL<=>RSX

VS units<=> PS units

CPU<=>GPU

Processor A<=>Processor B

etc...