On June 14th Toshiba did this presentation at 2007 VLSI Symposia.
http://www.vlsisymposium.org/circuits/cir_abstract/5-4.htm
http://www.vlsisymposium.org/circuits/technical.html
According to Tech-On report, this automatically compiled/designed version is 30% smaller than the original SPU but 10% slower. The 4Ghz clockspeed seems unusually high for this kind of synthesizable chip.
http://www.vlsisymposium.org/circuits/cir_abstract/5-4.htm
http://www.vlsisymposium.org/circuits/technical.html
Session 5-4
A Design Methodology Realize an Over GHz
Synthesizable Streaming Processing Unit
Abstract
A 7.07mm2 synthesizable Streaming Processing Unit (SPU) is fabricated in a 65nm CMOS technology with 8 level copper layers which is migrated from its original custom design to a synthesizable design to get higher design portability with small performance reduction. The logic area is 20% smaller in addition to process scaling factor. Correct functional operation is realized at frequencies 4GHz, 1.4V
According to Tech-On report, this automatically compiled/designed version is 30% smaller than the original SPU but 10% slower. The 4Ghz clockspeed seems unusually high for this kind of synthesizable chip.